1.8伏金氧半低雜訊放大器應用於超寬頻3.1-10.6GHZ無線接收端

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(1)國立交通大學電子工程學系電子研究所碩士班. 碩士論文. 論文題目: 1.8 伏金氧半低雜訊放大器應用於超寬頻 3.1-10.6GHZ 無線接收端 A 1.8 -V CMOS LNA applied for Ultra-Wideband 3.1 to 10.6GHZ Wireless Receivers 研究生：李秋峰指導教授：荊鳳德博士. 中華民國九十四年七月.

(2) 1.8 伏金氧半低雜訊放大器應用於超寬頻 3.1-10.6GHZ 無線接收端. A 1.8 -V CMOS LNA applied for Ultra-Wideband 3.1 to 10.6GHZ Wireless Receivers 研究生：李秋峰指導教授：荊鳳德. Student: Chiou-Feng Lee 博士. Advisor: Dr. Albert Chin. 國立交通大學電子工程學系. 電子研究所碩士班. 碩士論文 A Thesis Submitted to Department of Electronics Engineering & Institute of Electronics College of Electrical Engineering and Computer Science National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Master in Electronics Engineering. July 2005 HsinChu, Taiwan, Republic of China 中華民國九十四年七月.

(3) 1.8 伏金氧半低雜訊放大器應用於超寬頻 3.1-10.6GHZ 無線接收端. 研究生：李秋峰. 指導教授：荊鳳德教授國立交通大學電子工程學系暨電子研究所摘要. 本論文研製一個應用於超寬頻 3.1-10.6 GHZ 的低雜訊放大器是採用電感-電容階梯式做輸入匹配，而在輸出端是用 L-section 做匹配。本研究是以 0.18 微米互補式金氧半製程實現。此低雜訊放大器是以兩級放大為主架構，第一級為 CS-CG 堆疊結構，是為了改善逆向隔離 S12 及頻率響應，第二級為 Darlington pair 結構，可以增加單位增益頻寬 fT。為了能在所應用的頻段內達到相對的平坦增益，利用 shunt peaking 的方法去實現。供應電壓 VDD 為 1.8 伏特時，整個電路功率消耗約為 22mW，及包含 pad 的情況下整個電路大小約為 1 mm2。本研究的低雜訊放大器所量測的規格，平均順向增益(S21)約為 7dB，逆向隔離(S12)約為-35dB，S11 約為-7dB， S22 約為-8dB。而平均雜訊指數約為 8dB。. i.

(4) A 1.8 -V CMOS LNA applied for Ultra-Wideband 3.1 to 10.6GHZ Wireless Receivers. Student: C.F. Lee. Advisor: Dr. Albert Chin. Department of Electronics Engineering & Institute of Electronics National Chiao Tung University Abstract A 3.1-10.6 GHZ low noise amplifier is applied for ultra-wideband, it introduces LC ladder for input matching. And L section is used for output matching. This research is fabricated in 0.18-μm CMOS process. Two amplified stages are formed for main topology in low noise amplifier. The first stage introduces CS-CG cascode configuration, it can improve the reverse isolation and frequency response. The second stage introduce Darlington pair configuration, it can boost the unity gain bandwidth. Relatively flat gain is essential over the entire desired band. The low noise amplifier introduces the shunt peaking to achieve the above purpose. The total power dissipation of the chip is about 22 mW at power supply 1.8 volt. The chip size included pad is 1 mm2. The measurement result of this study expect that the average forward S21 is 7 dB, the reverse isolation S12 is -35 dB, the magnitude of S11 is -7 dB, the magnitude of S22 is -8 dB, and the noise figure is 8 dB.. ii.

(5) Acknowledgement In pursuing my studies, many people render their assistances. First, I would like to acknowledge my advisor, Professor Albert Chin, for beneficial edification and proper direction. I am also appreciation to ED633 Lab members. And finally I bless my mates, Jessie Tzeng, C. M. Lai, Gitime Lin, and C. F. Cheng, who have a brilliant expectation.. iii.

(6) Contents Abstract (in Chinese)…………………………………………………………………i Abstract (in English)…………………………………………………………………ii Acknowledgement…………………………………………………………………...iii Contents……………………………………………………………………………...iv Figure Captions………………………………………………………………………v. Chapter 1 Introduction 1.1 Motivation…………………………………………………………………………1. Chapter 2 Basic Concepts in RF Design 2.1 Nonlinear effect in RF circuits…………………………………………………….3 2.2 Noise……………………………………………………………………………….5 2.3 Cascaded nonlinear stages…………………………………………………………7. Chapter 3 Basic Low-Noise Amplifiers Design 3.1 General consideration in low-noise amplifiers…………………………………...12 3.2 Conventional LNA design………………………………………………………..17. Chapter 4 The Design of CMOS LNA for Ultra-wideband Wireless Receivers 4.1 Circuit topology and design flow………………………………………………...24 4.2 Layout and other consideration…………………………………………………..38. Chapter 5 Experimental Results and Discussion 5.1 Experimental Results……………………………………………………………..43 5.2 Discussion and Conclusion………………………………………………………43. References…………………………………………………………………………...48 Vita…………………………………………………………………………………...50. iv.

(7) Figure Captions Chapter 1 Introduction. Chapter 2 Basic Concepts in RF Design Fig. 2-1 (a) Definition of the 1-dB compression point, (b) Corruption of a signal due to intermodulation, (c) The third-order intercept point Fig. 2-2 Determination of input-referred noise voltage. Fig. 2-3 Representation of noise in a two-port network by equivalent input voltage and current sources. Fig. 2-4 Cascaded nonlinear stages.. Chapter 3 Basic Concepts in RF Design Fig. 3-1 Stability of two-port networks. Fig. 3-2 Block diagram of an amplifier. Fig. 3-3 Matching networks. Fig. 3-4 (a) A discrete RF amplifier; (b) the dc model; (c) the ac model. Fig. 3-5 Common source stage use inductance degeneration. Fig. 3-6 Wide-band LNA circuit schematic. Fig. 3-7. Another wide-band LNA schematic. Fig. 3-8. Small-signal equivalent circuit at the input. Fig. 3-9. Schematic circuit diagram of the cascade distributed amplifier. Fig. 3-10. A de-embedded m-derivedπ-equivalent.. Chapter 4 The Design of CMOS LNA for Ultra-wideband Wireless Receivers Fig.4-1. Proposed Low noise amplifier schematic. v.

(8) Fig. 4-2. (a) M1 noise sources. (b) Input-referred equivalent noise sources. (c) The part of the passive matching network. Fig.4-3. The power loss of passive network. Fig. 4-4. The equivalent circuit of the Z2 input impedance. Fig. 4-5. The equivalent circuit of the Zin input impedance. Fig. 4-6. The simulated S11 of the proposed LNA. Fig. 4-7. The Qn of the proposed LNA. Fig. 4-8. The simulated S22 of the proposed LNA. Fig. 4-9. The Darlington pair schematic. Fig.4-10. The simulation result of the Darlington pair compared with single transistor. Fig. 4-11. The model of shunt peaking amplifier. Fig. 4-12. The relationship of the value of m and ω1. Fig. 4-13. The layout diagram of the proposed low noise amplifier. Fig. 4-14. The equivalent circuit model of the inductor. Fig. 4-15. (a) Lg3 EM simulation v.s. Equivalent model. (b) Ld EM simulation v.s. Equivalent model. (c) Ls1 EM simulation v.s. Equivalent model. Fig. 4-16. The quality factor of the inductors in the low noise amplifier.. Chapter 5 Experimental Results and Discussion Fig. 5-1. (a) The measured forward gain of the low noise amplifier. (b) The measured reverse isolation of the low noise amplifier. Fig. 5-2. (a) The measured magnitude of S11 of the low noise amplifier. (b) The measured magnitude of S22 of the low noise amplifier. Fig. 5-3. The measured noise figure.. vi.

(9) Chapter 1 Introduction 1.1 Motivation Ultra-wideband (UWB) system is a new wireless technology capable of transmitting data over a wide spectrum frequency bands with very low power and high date rates. It communicates with short pulses on the order of nanoseconds, thus spreading the energy of the radio signal over a very wide bandwidth. Compared to traditional narrow band communication systems, UWB technology has the promising ability to provide high data rate at low cost with relatively low power consumption. The FCC has allocated 7.5 GHZ of spectrum for unlicensed use of UWB devices in the 3.1 to 10.6 GHZ frequency band. The low noise amplifier needs to amplify the received UWB signal with sufficient gain and as little as possible. From Shannon’s equation. C = B log(1 +. BS0 ) for the channel capacity, we know that a UWB wireless network, BN 0. the bandwidth will likely be much higher than the data rate, so that the system can operate at very low signal to noise ratio [1]. For the overwhelming majority DSP chips, most designer introduces the CMOS process to achieve system on chip (SOC). But for analog and radio frequency chips, due to the electricity, noise and other parameters have strict demands. In order to achieve the specification of the products, different communication systems have different demands in process. In the past, due to GaAs process has excellent high frequency parameters, so most designer introduces the GaAs process to design theirs products. But the deep sub-micro CMOS process has acceptable high frequency parameters. Recently there are designers introduce 0.25 micrometer, 0.18 micrometer or 0.13 micrometer CMOS process to design radio frequency transceivers. Because CMOS process’s cost is less. 1.

(10) expensive than other process’s. And that radio frequency transceiver introduces CMOS process is facile integration with base-band circuit. Achieving perfection of the SOC is feasible in future.. 2.

(11) Chapter 2 Basic Concept in RF Design 2.1 Nonlinear Effect in RF Circuits While many RF circuits can be approximated with a linear model to obtain their response to small signals, nonlinearities often lead to interesting and important phenomena. For simplicity, we assume that. y (t ) ≈ α1 x(t ) + α 2 x 2 (t ) + α 3 x 3 (t ). (1). If a sinusoid is applied to a nonlinear system, the output generally exhibits frequency components that are integer multiples of the input frequency. If x(t ) = A cos ωt , then. y (t ) = α1 A cos ωt + α 2 A2 cos 2 ωt + α 3 A3 cos 3 ωt =. α 2 A2 2. ⎛ 3α 3 A 3 ⎞ α 3 A3 α 2 A2 ⎟⎟ cos ωt + + ⎜⎜ α 1 A + cos 2ωt + cos 3ωt 4 2 4 ⎝ ⎠. (2). (3). In Eq. (3), then term with the input frequency is called the “fundamental” and the higher-order terms the “harmonics.” The amplitude of the nth harmonic consists of a term proportional to An. In (3) this occurs if. α 3 <0.. Written as α 1 +. 3α 3 A 2 , the gain is therefore a 4. decreasing function of A. In most circuits, the output is a “compressive” or “saturating” function of the input; that is, the gain approached zero for sufficiently high input levels. This effect is quantified by the “1-dB compression point,” defined as the input signal level that causes the small-signal gain to drop by 1 dB. If plotted on a log-log scale as a function of the input level, the output level falls below its ideal value by 1 dB at the 1-dB compression point.. 3.

(12) When two signals with different frequencies are applied to a nonlinear system, the output in general exhibits some components that are not harmonics of the input frequencies. Called intermodulation (IM), this phenomenon arises from multiplication of the two signals when their sum is raised to a power greater than unity. We assume that. x(t ) = A1 cos ω1t + A2 cos ω 2 t. (4). Thus,. y(t ) = α1 ( A1 cos ω1t + A2 cos ω2t ) + α 2 ( A1 cos ω1t + A2 cos ω2t ) 2 (5). + α 3( A1 cos ω1t + A2 cos ω2t )3 Expanding the left side and discarding DC terms and harmonics, we obtain the intermodulation products:. 3α A A 3α A A ω → 2ω1 ± ω 2 : 3 1 2 cos(2ω1 + ω 2 )t + 3 1 2 cos(2ω1 − ω 2 )t 4 4. (6). 3α A A 3α A A ω → 2ω 2 ± ω1 : 3 2 1 cos(2ω 2 + ω1 )t + 3 2 1 cos(2ω 2 − ω1 )t 4 4. (7). 2. 2. 2. 2. Because the difference between ω1 and ω2 is small, the components at 2ω1-ω2 and 2ω2-ω1 appear in the vicinity of ω1 and ω2. In a typical two-tone test, A1=A2=A, and the ratio of the amplitude of the output third-order products to α1A defines the IM distortion. If a weak signal accompanied by two strong interferers experiences third-order nonlinearity, then one of the IM products falls in the band of interest, corrupting the desired component. Use IP3 to characterize this behavior. Called the “third intercept point” (IP3), this parameter is measured by a two-tone test in which A is chosen to be sufficiently small so that higher-order nonlinear terms are negligible and the gain is relatively constant 4.

(13) and equal to α1. The third-order intercept point is defined to be at the intersection of the two lines [2].. 2.2 Noise Noise is usually generated by the random motions of charges or charge carriers in devices and materials. Because the noise process is random, one cannot identify a specific value of voltage at a particular time, and the only recourse is to characterize the noise with statistical measures, such as the mean-square or root-mean-square values. Because of having various noise sources in the circuit, we need to simplify calculation of the total noise at the output [3]. Obviously, the output-referred noise does not allow a fair comparison of the performance of different circuits because it depends on the gain. According the circuit theory, we can use the input-referred noise of circuits to represent the noise of behavior in the circuits. To overcome the above confusion, we specify the “input-referred noise” of circuits. Illustrate conceptually in Fig. 2-2. To represent the effect of all noise sources in the circuit by a single noise source. The input-referred noise and the input signal are both multiplied by the gain as they are processed by the circuit. Thus, the input-referred noise indicates how much the input signal is corrupted by the circuit’s noise. The input-referred noise is a spurious quantity in that in cannot be measured at the input of the circuit. The two circuits of Figs. 2-2(a) and (b) are equivalent in mathematics but the real physical circuit is still that in Fig. 2-2(b). The noise of a two-port network can be modeled by two input noise sources: a series voltage source and a parallel current source. Generally, the correlation between the two sources must be taken into account. The situation is shown in Fig. 2-3, where a two-port network containing noise sources is represented by the same network with internal noise sources removed and with a noise voltage and current source connected at the input. It can be shown that this representation is valid for any source impedance, provided that. 5.

(14) correlation between the two noise sources is considered [4]. The signal-to-noise ratio (SNR), defined as the ratio of the signal power to the total noise power, is an important parameter. In RF circuit, most of the front-end receiver blocks are characterized in terms of their “noise figure” rather than the input-referred noise. Noise figure has many different definitions. The most commonly accepted definition is noise figure =. SNRin , SNRout. (8). Noise figure is a measure of how much the SNR degrades as the signal passes through a circuit. If a circuit has no noise source, the SNRout=SNRin, regardless of the gain. The noise figure of a two-port amplifier is given by F = Fmin +. rn y s − yopt gs. (9). where rn is the equivalent normalized noise resistance of the two-port, ys=gs+jbs represents the normalized source admittance, and yopt=gopt+jbopt represents the normalized source admittance which results in the minimum noise figure, called Fmin. If we express ys and yopt in terms of the reflection coefficients Гs and Гopt. ys = yopt =. 1 − Γs 1 + Γs. (10). 1 − Γopt. (11). 1 + Γopt. Substitute (10) and (11) into (9) results in the relation F = Fmin +. 4rn Γs − Γopt. 2. 2. (1 − Γs ) 1 + Γopt. 2. (12). When Гs=Гopt occurs, the value of F is equal to Fmin. Fmin is a function of the device bias current and operating frequency [5]. For a cascade of stages, the overall noise figure can be obtained in terms of the NF and gain of each stage. For m-stages, the NFtot is equal to 6.

(15) NFtot = 1 + ( NF1 − 1) +. NF2 − 1 NFm − 1 +L+ Ap1 Ap1 L Ap ( m−1). (13). where Apm is the available power gain of the m-th stage. This is called the Friis equation. The Friis equation indicates that the noise contributed by each stage decreases as the gain preceding the stage increases, implying that the first few stages in a cascade are the most critical [2].. 2.3 Cascaded Nonlinear Stages Since in RF systems, signals are processed by cascaded stages, it is important to know how the nonlinearity of each stage is referred to the input of the cascade. Consider two nonlinear stages in cascade. As shown in Fig.2-4. Assuming that the input-output relationship is. y1 (t ) = α1 x(t ) + α 2 x 2 (t ) + α 3 x 3 (t ). (14). y2 (t ) = β1 y1 (t ) + β 2 y1 (t ) + β 3 y1 (t ) .. (15). 2. 3. Substitute (14) into (15) results in the relation y2 (t ) = α1β1 x(t ) + (α 3 β1 + 2α1α 2 β 2 + α1 β 3 ) x 3 (t ) 3. (16). . If we consider only the first- and third-order terms, then AIP 3 =. 4 α 1 β1 . 3 α 3 β1 + 2α1α 2β 2 + α13 β 3. (17). From equation (17) can be simplified if the two sides are inverted and squared: 1 A2 IP 3. =. 1 A2 IP 3,1. 3α 2 β 2 α + 21 , 2β 1 A IP 3, 2 2. +. (18). where AIP3,1 and AIP3,2 represent the input IP3 points of the first and second stages, respectively. From the above result, we note that as α1 increases, the overall IP3 decreases. This is because with higher gain in the first stage, the second stage senses larger input levels, thereby producing much greater 7.

(16) IM3 products [2].. 8.

(17) 20 log A out 1 dB. A1-dB. 20 log A in. (a) Interferers Desired Channel. LNA f. f (b). 20 log(α1A ) OIP3 20 log(¾α 3A3 ) IIP 3. 20 log A. (c) Fig. 2-1 (a) Definition of the 1-dB compression point, (b) Corruption of a signal due to intermodulation, (c) The third-order intercept point. 9.

(18) In 21. Vn. 2. Vn 2 ,out. 2. (a). Vn 2 ,in. Vn 2 ,out (b) Fig. 2-2 Determination of input-referred noise voltage.. Noisy network. Rs. (a). vi. Rs. 2. ii. Noiseless network. 2. (b) Fig. 2-3 Representation of noise in a two-port network by equivalent input voltage and current sources.. 10.

(19) IIP3,1. IIP3,2. Fig. 2-4 Cascaded nonlinear stages.. 11.

(20) Chapter 3 Basic Low-Noise Amplifiers Design 3.1 General consideration in Low-Noise Amplifiers The stability of an amplifier is a very important consideration in a design and can be determined from the S parameters, the matching networks, and the terminations. A two-port network to be unconditionally stable can be derived from (19) to (22). Γs < 1. (19). ΓL < 1. (20). ΓI N = S11 +. S12 S 21ΓL <1 1 − S 22 ΓL. (21). ΓOUT = S 22 +. S12 S 21Γs <1 1 − S11ΓS. (22). The two-port network is shown in Fig. 3-1. For unconditional stability any passive load or source in the network must produce a stable condition. The solution of (19) to (22) gives the required conditions for the two-port network to be unconditionally stable []. 2. k=. 2. 1 − S11 − S 2 2 + Δ. 2. 2 S12 S 21 Δ = S11S 22 − S12 S 21. (23) (24). A convenient way of expressing the necessary and sufficient conditions for unconditional stability is k >1. (25). Δ < 1.. (26). 12.

(21) The need for matching networks arises because amplifiers, in order to deliver maximum power to a load or to perform in a certain desired way, must be properly terminated at both the input and the output ports. Figure 3.2 illustrates a typical situation in which a transistor, in order to deliver maximum power to the 50-ohm load, must have the terminations ZS and ZL. The input matching network is designed to transform the generator impedance to the source impedance ZS, and the output matching network transforms the 50-ohm termination to the load impedance ZL. In a resonant circuit, the ratio of its resonant frequency fo to its bandwidth is known as the loaded Q of circuit. That is,. QL =. ωo BW. (27). The matching networks in Fig. 3-3 are used to provide a match at a certain frequency. The frequency response of a matching network can be classified as either a two-pole low-pass filter or a high-pass filter. At each node of the matching networks, there is an equivalent series input impedance, denoted by RS+jXS. Hence, a circuit node Q, denoted by Qn, can be defined at each node as. Qn =. XS RS. (28). If the equivalent parallel input admittance at the node is GP+jBP, the circuit node Q can be expressed in the form. Qn =. BP GP. (29). In order to obtain a high value of QL, the circuit node Q must be high. Higher values of QL than those obtained with the matching networks in Fig 3-3 can be obtained using matching circuits with three elements. The addition of a third element to a matching networks in Fig 3-3 results in either the lossless Tee network or the lossless Pi network. The addition of a third element introduces flexibility in the selection of the loaded Q, since the equivalent series impedance at the nodes in the circuit will determine various 13.

(22) values of Qn. Obviously, a high value of Qn in the circuit will result in a high value of QL. However, it is not simple to exactly relate Qn to QL in these circuits. The Q of a Tee or Pi network is normally taken as the highest value of Qn in the circuit. The upper and lower parts of the constant-Q contours can be shown to satisfy a circle equation as follows. Since z = r + jx =. 1+ Γ 1−U 2 −V 2 2U = + j 2 2 1 − Γ (1 − U ) + V (1 − U ) 2 + V 2. (30). then. Qn =. x 2U = r 1−U 2 −V 2. (31). which can be written as 2. ⎛ 1 ⎞ 1 ⎟⎟ = 1 + 2 U + ⎜⎜V ± Qn ⎠ Q n ⎝ 2. (32). The plus sign applies when x is positive, and the minus sign when x is negative. Equation (32) is recognized as the equation of a circle. For x>0, the center in the Г plane is at (0, -1/Qn), and for x<0 at (0, 1/Qn); the radius of the circle is 1+. 1 Q2n. (33). In a RF amplifier, the input and output matching networks provide the appropriate ac impedances to the transistor. The transistor must also be biased at an appropriate quiescent point. A complete RF amplifier contains both dc bias components and the ac matching network. RFCS, bypass capacitors, and coupling capacitors need to be introduced so the dc bias components do not affect the ac performance of the amplifier. Illustrate conceptually in Fig. 3-4. [5]. 14.

(23) Zs. ΓOUT ΓL. Γs ΓIN. Two-port network. ES. ZL. ZOUT. ZIN. Fig. 3-1 Stability of two-port networks.. ZS=50Ω. Input matching network. E. Input matching network. ZS. Input matching network. ZL=50Ω. ZL. Fig. 3-2 Block diagram of an amplifier.. C. L ZLOAD. C. L. L. C L. ZLOAD. ZLOAD. C. Fig. 3-3 Matching networks.. 15. ZLOAD.

(24) V CC RC. R1. C2. RFC RFC C1. L2 L1. 50Ω VS. RFC. CB. CB RE. R2. 50Ω. CE. (a). VCC R1. RC. R2. RE. (b). C2 C1 50Ω. L2. L1. 50Ω. VS. (c) Fig. 3-4 (a) A discrete RF amplifier; (b) the dc model; (c) the ac model. 16.

(25) 3.2 Conventional LNA design 3.2.1 Narrow band LNA design In the design of low noise amplifier, there are many important goals. These include noise figure minimization, providing sufficient gain with good linearity, and the reasonable power consumption. Fig 3-5 illustrates the input stage of the low noise amplifier with source degeneration. A simple calculation is. Z in = s ( Lg + Ls ) +. ⎛g ⎞ 1 + ⎜ m 2 ⎟ Ls sC gs 2 ⎜⎝ C gs 2 ⎟⎠. (34). If choose appropriate value of inductance and capacitance, then Lg+Ls and Cgs will resonate at certain frequency. By choosing Ls appropriately, the real term can be made equal to 50Ω. The gate inductance Lg is used to set the resonance frequency once Ls is chosen to satisfy the criterion of a 50Ω input impedance. The matching method in noise performance is better than using resistance termination of the input end. The reverse isolation of low noise amplifier determines the amount of LO signal that leaks from the mixer to the antenna. The leakage arises from capacitive paths, substrate coupling, and bond wire coupling. In heterodyne receivers with a high first IF, the image-reject filter and the front-end duplexer significantly suppress the leakage because the LO frequency falls in their stop-band. In homodyne topology, the leakage is attenuated primarily by the LNA reverse characteristics. Equation (23) suggests that stability improves as S12 decrease, i.e., as the reverse isolation of the circuit increases. The feedback can be suppressed through the use of a cascade configuration, but at the cost of a somewhat higher noise figure. The common-gate transistor in the Fig 3-5, M1, plays two important roles by increasing the reverse isolation of the LNA: (1) it lowers the LO leakage produced by the following mixer, and (2) it improves the stability of the circuit by minimizing the feedback from the output to the input [6].. 17.

(26) M1. Lg. M2. ZIN Ls. Fig. 3-5 Common source stage use inductance degeneration. VDD. VDD. L1. Lf. Rf. Cf. L2. C2 M1. V G1 M2. 50Ω. C1. R bias VG2. E. Fig. 3-6 Wide-band LNA circuit schematic.. 18. C3 RL.

(27) 3.2.2 wide-band LNA design Figure 3-6 is the LNA circuit schematic. We discuss this circuit step by step from the first stage. First, to make 1 / g m = 50Ω , the gm value of common gate amplifier is going to be fixed at certain trans-conductance. An additional stage is required to provide sufficient gain over the desired band. A shunt feedback common source amplifier is used in the second stage for this purpose. The first step is the selection of transistor size and bias condition of the M1 to yield Re Z11 = 1 / g m = 50Ω . This ensures input matching condition for wide-band of frequency. But this condition is violated with optimum noise condition. There is a trade-off between noise and impedance matching in the LNA circuit. One of the major problems in the wide bandwidth amplifier design is the limitation imposed by the gain-bandwidth product of the active device. We know that any active device has a gain roll off at high frequency because of the gate-drain and gate-source capacitance in the transistor. This effect degrades the forward gain as the frequency increases and eventually the transistor stops functioning as an amplifier at the high frequency. Therefore the second design step is the selection of optimal bias point of second stage of LNA so that it operates at its maximum fT. In addition to this S 21 degradation with frequency other complications that arises in wide-bandwidth amplifier design includes, increase in reverse gain S12 and noise figure at high frequency. Negative feedback configuration is used to reduce these effects and increase the bandwidth. An inductor L is connected in series with Rf such that after certain frequency the negative feedback decreases in proportion to the S21 roll-off. This technique improves gain flatness at high frequency. The load inductance of L1 and L2 replace the resistor load which is used conventionally. The magnitude of the inductor’s impedance increases as frequency increases. This increase inductor impedance compensates the active device gain degradation that occurs at high frequency [7]. 19.

(28) Another wide-band LNA design schematic is shown in Fig. 3-7. In figure 3-7, the. Rf is added as a shunt feedback element to the conventional cascade narrow band LNA and Lload is used as shunt peaking inductor at the output. The capacitor Cf is used for the ac coupling purpose. The source follower, composed of M3 and M4, is added for measurement proposes only, and provides wideband output matching. C1 and C2 are ac coupling capacitor. The small-signal equivalent circuit at he input of the LNA is shown in Fig. 3-8. The resistor R fM = R f /(1 − Av ) represents the Miller equivalent input resistance of Rf, where Av is the open-loop voltage gain of the LNA. From equivalent circuit, the value of Rf can be much larger than that of the conventional resistance shunt-feedback. In the conventional resistance shunt-feedback, the size of Rf is limited as RfM determines the input impedance. One of the key roles of the feedback resistor Rf is to reduce the Q-factor of the resonating narrowband LNA input circuit. The Q-factor of the circuit shown in Fig. 3-8 can be approximately given by QWB ≈. 1 ⎡ (ω0 Lg ) 2 ⎤ ⎢ RS + ωT LS + ⎥ • ω0 • C gs R fM ⎦⎥ ⎣⎢. .. (35). From equation (35), and considering the inversely linear relation between the -3dB bandwidth and the Q-factor, the narrowband LNA in Fig. 3-7 can be converted into a wideband amplifier by the proper selection of Rf. To design a wideband amplifier that covers a certain frequency band, the narrowband amplifier will be optimized at the center frequency. The feedback resistor Rf also provides its conventional roles of flattening the gain over a wider bandwidth of frequency with much smaller noise figure degradation [8].. 20.

(29) VDD. VDD. Lload Rload M4 Rf. Lg. Vg2. Cf. IN C1. OUT. M2 C2. M3. M1 Rbias Ls Vg1. Fig. 3-7. Another wide-band LNA schematic.. RS. Lg. Cgs. ωT Ls RfM Ls. Fig. 3-8. Small-signal equivalent circuit at the input.. 21.

(30) Another circuit topology for wide-band application is distributed amplifier (DA). Distributed amplifier was first introduced by [9]. MMIC DA was mainly implemented using GaAs-based or SiGe devices. The distributed amplifier schematic is shown in Fig. 3-9. From the Fig. 3-9, we can observe that the power gain of a cascade pair is considerably higher than that of a common-source single transistor. The input signal propagates down the gate line, with each FET tapping off some of the input power. The amplified output signals from the FETs form a traveling wave on the drain line. The propagation constants and lengths of the gate and drain lines are chosen for constructive phasing of the output signals, and the termination impedanc3es on the lines serve to absorb waves traveling in the reverse directions. According to equivalent circuit of a single unit cell of the gate line and drain line, we can get optimal number of section [10].. N opt =. ln(α g l g / α d ld ). α g l g − α d ld. (36). A small resistor Rgx is added in the gate of common-gate transistor to improve the entire circuit stability. The input and output impedances of the cascade device are needed. In the DA design, the input and output of the cascade FETs used in the distributed amplifier were terminated by the gate line characteristic impedance Zog and drain line characteristic impedance Zod, respectively. Higher gain can be obtained by choosing higher characteristic impedance of gate (Zog) and drain lines (Zod) but the cutoff frequency will be lower, which will limit the bandwidth. The m-derived matching section is used in our design to overcome the well-known non-constant image impedance from the constant-k sections. A de-embedded m-derived πequivalent circuit is shown in Fig. 3-10. Distributed amplifiers are not capable of very high gains or very low noise figure, however, and generally are larger in size than an amplifier having comparable gain over a narrower bandwidth. 22.

(31) VG2 VDD. Output Rgx. Rgx. R gx. VG1 Input. M-Derived matching section. Fig. 3-9. Schematic circuit diagram of the cascade distributed amplifier.. mZ1 2Z2 /m ⎛ 1 − m2 ⎞ 2⎜ Z1 ⎟ ⎝ 4m ⎠. Fig. 3-10. A de-embedded m-derivedπ-equivalent.. 23.

(32) Chapter 4 Ultra-Wideband CMOS LNA Design 4.1 Circuit topology and Design flow 4.1.1 Overall circuit introduction Figure 4-1 shows the proposed ultra-wideband CMOS low noise amplifier topology. From Fig. 4-1, we can observe that it is a two stage low noise amplifier. Where, the output stage is formed by Darlington pair. Because any MOSFET has a property of gain decreases as frequency increases. The parameter ωT represents the gain-bandwidth frequency. It is the frequency where the short circuit gain approximates unity. So, it is expected that the parameter ωT can decide high frequency performance. Device fT is bounded within any given technology, so it would seem that once biasing conditions that maximize fT have been established. Equation (37) represents the fT. 2πf T =. gm C g s + C gd. (37). Briefly speaking, fT is the ratio of trans-conductance to input capacitance. If a way could be found to, say, decreasing trans-conductance, fT would increase. The ordinary differential pair may be considered an fT doubler by this definition, for the device capacitances are in series as far as a differential input is concerned. Hence, the differential input capacitance is one half that of each transistor. The differential trans-conductance, on the other hand, is unchanged because, although the input voltage divides equally between the two transistors, the differential output current is twice the current in each device. Hence, the overall stage trans-conductance is equal to that of each transistor, and a doubling of fT results [3]. The ultra-wideband is for 3.1 to 10.6 GHZ application. The flat forward gain over the whole bandwidth is essential. A technique that satisfied this requirement of large. 24.

(33) bandwidth at low cost is known as shunt peaking. The resistance Rd improves the gain at lower frequency. At high frequency, the Ld can improve the gain. L-section matching network is used for measurement purposes to drive an external 50 Ω load. And Cin and Cout is AC coupling capacitor. Between the first and second stage is Cinter-stage that block the DC bias point and provide an AC path from the first stage to next stage. The cascode topology improves the reverse isolation (S12) and the frequency response of the amplifier. Because the M2 of the cascode topology has the small input impedance, it can yield the small Miller capacitor. The cascode component is chosen as small as possible to reduce the parasitic capacitors.. 4.1.2 Noise analysis The noise contribution of the input network is due to the finite quality factor Q of the integrated inductors. The MOSFET transistor noise sources are shown in figure 4-2. In reference [11], the noise generator i 2 d is I aD ⎛2 ⎞ i 2 d = 4kT ⎜ g m ⎟Δf + k Δf , f ⎝3 ⎠. (38). I aD ⎛2 ⎞ Δf is flicker noise where 4kT ⎜ g m ⎟Δf is thermal noise component, and k f ⎝3 ⎠. component. And noise generator i 2 g is i 2 g = 2qI G Δf .. (39). As shown in figure 4-2 (b), because the current gain of the source degeneration is. β ( jω ) =. ωT g , and the cut frequency is ωT ≈ m , so the i 2 n is jω C gs i2n = i2 g +. jωC gs gm. i2d ,. (40). and v 2 n is v 2 n = Z i 2 g + (1 − ω 2C gs Z ) 25. i2d , gm. (41).

(34) VDD =1.8 volts. V DD=1.8 volts. Ld. Ld. Rd. Rd. LO. Cinter-stage. Output CO. M3 RG. M2. M4 R bias. L g2. DC. L g3. V G2. M1 RFin. C1. L g1 DC. C2 L s1. VG1 Cs. L s2. Fig.4-1. Proposed Low noise amplifier schematic.. M1 i2d. i2g. Ls1 Cs. Ls2. (a). 26.

(35) v2n. M1. i 2n. Ls1 Cs. Ls2. (b). NF=Loss. Y1. Lg1. Y2. Z. Lg2. Lg3. C1. C2 Y3. (c) Fig. 4-2. (a) M1 noise sources. (b) Input-referred equivalent noise sources. (c) The part of the passive matching network. 8 Square:Ideal component simulated Circle:Equivalent model simulated Triangle:Equation Calculated Star:Noise Figure. Loss(dB). 6. 4. 2 0. 2. 4. 6. 8. 10. 12. Frequency(GHZ). Fig.4-3. The power loss of passive network. 27.

(36) where Z is Z = jωLs1 +. jωLs 2 . 1 − ω 2Cs Ls 2. (42). For a lossy passive reciprocal network the noise figure is equal to the loss [10]. The noise contribution of the passive network in the figure 4-2 (c) is. (. ). (43). A + B / 50 − 50C − D , A + B / 50 + 50C + D. (44). 2. 10 log 1 − S11 − S 21. 2. where S11 is equal to. and S21 is equal to 2 . A + B / 50 + 50C + D. (45). The transmission matrix parameters [10] A is equal to 1 − ω 2 C 2 Lg 2 ,. (46). jωLg 3 (1 − ω2C2 Lg 2 ) + jωLg 2 ,. (47). and B is equal to. and C is equal to jωC2 +. 1 − ω 2C1 Lg1 j ωL g 1. (1 − ω C L ), 2. 2. (48). g2. and D is equal to. ⎤ ⎡ 1 − ω 2C1 Lg1 L jωLg 3 ⎢ jωC2 + 1 − ω 2C2 Lg 2 ⎥ + 1 + g 2 1 − ω 2C1 Lg1 . jωLg1 Lg1 ⎥⎦ ⎣⎢. (. ). (. ). (49). The loss of the passive network is shown in figure 4-3.. 4.1.3 Input matching and output matching The input impedance of the MOS transistor with the inductive source degeneration is a series RLC circuit. The input impedance Z2 is. 28.

(37) Z 2 = s (Lg 3 + Ls1 ) +. ⎞ Ls 2 sLs 2 g ⎛ 1 ⎟. + + m1 ⎜⎜ Ls1 + 2 2 sC gs1 1 + s Cs Ls 2 C gs1 ⎝ 1 + s C s Ls 2 ⎟⎠. (50). And the parallel impedance Z1 is. Z1 =. sLg1 1 + s 2C1 Lg1. .. (51). Figure 4-4 shows the two port network for calculating input impedance. Y1 =. A = 1+. 1 1 + sC2 Z 2 1 , Y2 = , Y3 = Z1 Z2 sLg 2. 1 Y2 YY Y , B = , C = Y1 + Y2 + 1 2 , D = 1 + 1 Y3 Y3 Y3 Y3. (52) (53). According to transmission matrix theory, we can find the input impedance from ABCD parameters. ⎛ (1 + sC2 Z 2 ) sLg 2 ⎞ ⎟⎟ sLg 2 × ⎜⎜1 + Z2 AB ⎝ ⎠ Z in = = sL (1 + sC2 Z 2 ) ⎞ CD ⎛ sLg 2 ⎞ ⎛ 1 Z2 ⎜⎜1 + ⎟⎟ × ⎜⎜ + ⎟⎟ + g2 Z1 ⎠ ⎝ Z1 1 + sC2 Z 2 Z1 Z 2 ⎝ ⎠. (54). The Z2 involves the real part and imaginary part. The real part of the Z2 is dependant of the operation frequency. Because in reference[6], the real part of the input impedance is. gm Ls . Assume that the inductance of the Ls has fifteen percent error due to the C gs. process variation. The real part of the input impedance would have fifteen percent error. But in equation (50), the real part of the Z2 would have only six percent error. It proves that the LC parallel network in series at the source would reduce the real part of the input impedance error. The output impedance Rout of the Darlington pair is Rout = [Rbias + (1 + g m3 Rbias )ro 3 ] // ro 4 ≈ ro 4 .. (55). Because the real part of the impedance is ro2 parallel Rd, but the value of ro2 is larger than Rd. So the real part of the output impedance is about Rd. Choosing proper the value. 29.

(38) of the Rd, can reach purpose of the output matching. The imaginary part of the output impedance is ⎡ ⎛ sLd R ⎞ ⎞⎤ sLd ⎛ . // ⎢ sCds 3 // ⎜⎜ sC gs 4 + sC gd 4 ⎜1 + g m 4 d ⎟ ⎟⎟⎥ = 2 1 + s Cds 4 Ld ⎣ 2 ⎠ ⎠⎦ 1 + s 2CT Ld ⎝ ⎝. (56). And the L-section method is used for cancel the imaginary part of the output impedance over the entire operation band.. 4.1.4 Darlington pair The schematic is shown in Fig. 4-9. By proper choosing size of the transistor, the overall trans-conductance is Gm =. gm4 ≈ 0.9 g m 4 , ⎛ 1 ⎞ ⎜⎜1 + ⎟⎟ ⎝ g m3 Rbias ⎠. (57). and the overall parasitic capacitance is C gs 3 • C gs 4 C gs 3 + C gs 4. + C gd 3 + C gd 4 ≈ 0.5(C gs 4 + C gd 4 ) ,. (58). so the fTD would. fTD =. Gm 0.9 g m 4 ≈ ≈ 1.8 fTS . C gs 3 • C gs 4 0.5(C gs 4 + C gd 4 ) + C gd 3 + C gd 4 ) 2π ( C gs 3 + C gs 4. (59). Then, the overall cut-frequency would approximately twice with single transistor at same power consumption level. With fT doubling circuits it is often possible to obtain 80% increase in bandwidth, although the exact improvement depends on numerous and variable factors. The simulation result is shown in figure 4-10. From simulation result we can observe that the fT is similar, but the gain of the Darlington pair in the desired frequency band is higher than single transistor’s gain.. 30.

(39) Z2. Lg3 C gs1. gm1 Vgs. Ls1. Cs. Ls2. Fig. 4-4. The equivalent circuit of the Z2 input impedance.. Zin. Y 3=1/sL g2 Z2. Y1 =1/Z1. C2 Y2 =(sC2+1/Z 2)-1. Fig. 4-5. The equivalent circuit of the Zin input impedance.. 31.

(40) 1.0j 0.5j. 2.0j. 5.0j. 0.5j. 1.0j. 2.0j. 5.0j. -5.0j. -0.5j. -2.0j -1.0j. Fig. 4-6. The simulated S11 of the proposed LNA.. 1.0. 0.8. Qn. 0.6. 0.4. 0.2. 0.0. 4. 6. 8. Frequency(GHZ) Fig. 4-7. The Qn of the proposed LNA.. 32. 10.

(41) 1.0j 0.5j. 2.0j. 5.0j. 0.5. 1.0. 2.0. 5.0 -5.0j. -0.5j. -2.0j -1.0j. Fig. 4-8. The simulated S22 of the proposed LNA. Drain. Gate. M3. M4. I BIAS. Source. Fig. 4-9. The Darlington pair schematic.. 33.

(42) 40 Square:Darling pair Circle:Single transistor. Gain(dB). 32. 24. 16. 8. 0. 0.1. 1. 10. 100. Frequency(GHZ). Fig.4-10. The simulation result of the Darlington pair compared with single transistor.. 34.

(43) 4.1.5 Shunt peaking A model of shunt peaking amplifier is shown in Fig. 4-11. The capacitance C may be taken to represent all the loading on the output node, including that of a subsequent stage. The resistance R is the effective load resistance at that node and the inductor provides the bandwidth enhancement. It’s clear from the model that the transfer function vout. iin. is just the impedance of the RLC network, so it should be straightforward to. analyze. The addition of an inductance in series with the load resistor provides an impedance component that increases with frequency, which helps offset the decreasing impedance of the capacitance, leaving net impedance that remains roughly constant over a broader frequency range than that of the original RC network. The impedance of the RLC network may be written as Z ( s ) = (sL + R ) //. 1 . sC. (60). In addition to a zero, there are two poles. We introduce a factor m, defined as the ratio of the RC and L/R time constant: RC L/ R. (61). R[ s ( L / R)] + 1 R(τs + 1) = 2 2 , 2 s LC + sRC + 1 s τ m + sτm + 1. (62). m= Then, the transfer function becomes Z (s) = where τ =L/R.. The magnitude of the impedance, normalized to the DC value as a function of frequency, is then Z ( jω ) (ωτ ) 2 + 1 , = (1 − ω 2τ 2 m) 2 + (ωτm) 2 R. so that. 35. (63).

(44) ω = ω1. (−. m2 m2 + m + 1) 2 + m 2 + (− + m + 1) , 2 2. (64). where ω1 is the uncompensated -3dB frequency. If chose m = 2 ≈ 1.414 , then can extend the bandwidth to a value about 1.85 times as large as the uncompensated bandwidth. However, this choice of m leads to nearly a 20% peak in the frequency response, a value often considered undesirably high. If chose m = 1 + 2 ≈ 2.414 , then can lead to a bandwidth that is about 1.72 times as large as the un-peaked case. Hence, at least for the shunt-peaked amplifier, both a maximally flat response and a substantial bandwidth extension can be obtained simultaneously. In my design, the m is about 2.31, then ω ≈ 1.743ω1 .. 36.

(45) Vout L. i in. C R. Fig. 4-11. The model of shunt peaking amplifier. 1.9. w(w1). 1.8. 1.7. 1.6. 1.5 0.0. 0.8. 1.6. 2.4. 3.2. m. Fig. 4-12. The relationship of the value of m and ω1.. 37. 4.0.

(46) 4.2 Layout and Other Consideration 4.2.1 Layout consideration Figure 4-13 is the layout diagram. The measurement instruments have the parasitic loading effect. To avoid the effect we must parallel the bypass capacitor with the bias pad to ground. The parallel bypass capacitor can provide a short path to ground at high frequency. The parallel bypass capacitor requires essential capacitance so that make a result of ground at high frequency. The discontinuities introduce parasitic capacitance or inductance that can lead to phase and amplitude errors, input and output mismatch, and possibly spurious coupling. One approach for eliminating such effects is to construct an equivalent circuit for the discontinuity, including it in the design of the circuit, and compensating for its effect by adjusting other circuit parameters. Another approach is to minimize the effect of a discontinuity by compensating the discontinuity directly, often by chamfering of mitering the conductor. The right-angle bend can e compensated by mitering the cornet, which has the effect of reducing the excess capacitance at the bend. The technique of mitering can also be used to compensate step and T-junction discontinuities.. 4.2.2 Inductors implementation This design is fabricated by TSMC CMOS 0.18μm process. Because that this process there is not providing inductor model beyond 6 GHZ. In this design, inductors are essential components. Then, I use EM simulator to generate inductor model and size parameters. But CMOS process is silicon based substrate, the coupling effect is critical. And the EM simulator is not accurate enough for estimating coupling loss effect. In reference [12], it provides more accurate equation to estimate inductance and quality factor by physical size. So we can use equation and EM simulator to design inductors simultaneously. The size parameters of the inductor has four parameters, i.e. turns of. 38.

(47) number, space between two metal lines, width of the metal line and inner radius. When we get the inductors’ S-parameters, then use equivalent circuit model to obtain the components parameters. Use the obtained components parameters to place into the low noise amplifier circuit. Therefore we can get the result of post-simulation with inductors. Considering the cross coupling effect between two inductors and other components, must place inductor a distance from other components. The inductor equivalent circuit model is shown in figure 4-14.. 39.

(48) Fig. 4-13. The die diagram of the proposed low noise amplifier.. Cp Port1. Rs. L. Cox. Cox C sub. Port2. Csub. Rsub. Rsub. Fig. 4-14. The equivalent circuit model of the inductor.. 40.

(49) 1.0j 2.0j. 0.5j. 5.0j Square:S12 Circle:S11 0.5. 1.0. 2.0. 5.0. Open:EM simualted Solid:Equivalent Model -5.0j. -2.0j. -0.5j -1.0j. (a). 1.0j 0.5j. 2.0j. 5.0j. 0.5. 1.0. 2.0. 5.0. Square:S12 Circle:S11 Open:EM simulated Solid:Equivalent Model. -5.0j. -0.5j. -2.0j -1.0j. (b). 41.

(50) 1.0j 0.5j. 2.0j. 5.0j Square:S12 Circle:S11 0.5. 1.0. 2.0. 5.0. Open:EM simulated Solid:Equivalent Mode -5.0j. -0.5j. -2.0j -1.0j. (c) Fig. 4-15. (a) Lg3 EM simulation v.s. Equivalent model. (b) Ld EM simulation v.s. Equivalent model. (c) Ls1 EM simulation v.s. Equivalent model.. 30 Lg1 Lg3. 25. Ld Lo. 20. Ls1. Q. Ls2 Lg2. 15 10 5 0. 0. 5. 10. 15. 20. Frequency(GHZ) Fig. 4-16. The quality factor of the inductors in the low noise amplifier.. 42.

(51) Chapter 5 Experimental Result and Discussion 5.1 Experimental Result Figure 5-1 is simulated forward gain and reverse isolation respectively. The average forward gain is about 7dB and the reverse isolation is below -35dB at high frequency band. And the forward gain is flat in entire operation frequency band. Figure 5-2 is simulated S11 and S22 of the low noise amplifier. The average magnitude of the S11 is about -12dB and S22 is about -7dB in entire operation frequency band, respectively. Figure 5-3 is simulated noise figure of the low noise amplifier. The average noise figure is about 8dB in entire operation frequency band. The total power consumption is about 22mW with a power supply of 1.8 volts. And the die area including the pads is 1 mm2.. 5.2 Discussion and Conclusion From result of the figure 5-1 (b), we can observe that when the operation frequency is increasing, the magnitude of the S12 is increasing. Because the gate-drain capacitors (Cgd) provide a feedback path from drain end of MOSFET to gate end of MOSFET at high frequency. And since the silicon substrate coupling effect, the conductive silicon substrate provides a conductive path. The result of flat gain is caused by shunt peaking. The bandwidth is very extensive due to using Darlington pair as output stage. The magnitude of input reflection coefficient S11 is below -7dB. There are two resonance points at 3.5 GHZ, and 8.5 GHZ, respectively. The magnitude of output reflection coefficient S22 is below -7dB. Because the reactance of the output stage is smaller than input stage, the output stage can introduce little components to reach matching. At low frequency, the reactance isn’t effective, and the resistance is 43.

(52) dominant. The noise figure of the low noise amplifier is about 8dB. Because that input matching network introduce much passive components to reach matching. The passive component between input source and MOSFET gate end can cause noise degrade. The figure 4-3 shows the situation. But for the purpose of input matching, we need considerable passive components to form matching network. And the inductor is introduced greatly in my design. Because of the silicon substrate loss may cause noise coupling through large size inductors.. 44.

(53) 10. 8. S21(dB). 6. 4. 2. 0. 0. 2. 4. 6. 8. 10. 12. Frequency(GHZ). (a) -30. -33. S12(dB). -36. -39. -42. -45. 2. 4. 6. 8. 10. 12. Frequency(GHZ). (b) Fig. 5-1. (a) The measured forward gain of the low noise amplifier. (b) The measured reverse isolation of the low noise amplifier.. 45.

(54) 0. -5. S11(dB). -10. -15. -20. -25. 2. 4. 6 8 Frequency(GHZ). 10. 12. (a) 0. -3. S22(dB). -6. -9. -12. -15. 0. 2. 4. 6. 8. 10. 12. Frequency(GHZ). (b) Fig. 5-2. (a) The measured magnitude of S11 of the low noise amplifier. (b) The measured magnitude of S22 of the low noise amplifier.. 46.

(55) 16. NF(dB). 12. 8. 4. 0. 2. 4. 6. 8. Frequency(GHZ). Fig. 5-3. The measured noise figure.. 47. 10. 12.

(56) References [1] P. Heydari, “Design Considerations for Low-Power Ultra Wideband Receivers,” IEEE Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on 21-23 March 2005 Page(s):668 - 673 [2] B. Razavi, RF Microelectronics, 1st ed. NJ, USA: Prentice-Hall PTR, 1998. [3] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 1st ed. New York: Cambridge Univ. Press, 1998. [4] B. Razavi, Design of Analog CMOS Integrated Circuits, International ed. NY: McGraw Hill Co. 2001. [5] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design, 2nd ed. NJ: Prentice-Hall, Inc. 1997. [6] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHZ CMOS Low Noise Amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp; 745-759, May, 1997. [7] S. Vishwakarma, S. Jung and Y. Joo, “Ultra Wideband CMOS Low Noise Amplifier with Active Input Matching,” IEEE Ultra Wideband Systems, 2004. Joint with Conference on Ultrawideband Systems and Technologies. Joint UWBST & IWUWBS. 2004 International Workshop on 18-21 May 2004, pp. 415-419. [8] C-W. Kim, M-S. Kang, P. T. Anh, H-T. Kim and S-G. Lee, “An Ultra-Wideband CMOS Low Noise Amplifier for 3-5-GHZ UWB System,” IEEE J. Solid-State Circuits, vol. 40, no. 2, February, 2005. [9] R-C. Liu, K-L. Deng, and H. Wang, “A 0.6-22-GHZ broadband CMOS distributed amplifier,” in IEEE Radio Frequency Integrated Circuits Symp. Dig. Papaers, 2003, pp. 103-106 [10] D. M. Pozar, Microwave Engineering, 2nd ed. Crawfordsville: John Wiley & Sons, Inc. 1998. [11] P. R. Gary, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of. 48.

(57) Analog Integrated Circuits, 4th ed. Crawfordsville: John Wiley & Sons, Inc. 2001. [12] C. P. Yue, C. Ryu, J. Lau, T. H. Lee, and S. S. Wong, “A physical model for planar spiral inductors on silicon,” IEEE, Electron Devices Meeting, 1996. International 8-11 Dec. 1996 pp. 155-158. [13] A. Bevilacqua, and A. M. Niknejad, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6-GHZ Wireless Receivers,” IEEE J. Solid-State Circuits, vol.39, no. 12. December 2004. [14] J. N. Burghartz, D. C. Edelstein, H. A. Ainspan, and K. A. Jenkins, “RF Circuit Design Aspects of Spiral Inductors on Silicon,” IEEE J. Solid-State Circuits, vol.33, no. 12. December 1998. [15] H. Dedieu, C. Dehollain, J. Neirynck, and G. Rhodes, “A New Method for Solving Broadband Matching Problems,” IEEE Tran. Circuits and Systems, vol. 41, no. 9. September 1994. [16] H. J. Carlin, and P. Amstutz, “On Optimum Broad-Band Matching,” IEEE Tran. Circuits and Systems, vol. 28, no. 8. May 1981.. 49.

(58) Vita 姓名：李秋峰性別：男出生年月日：民國 68 年 9 月 23 日籍貫：台灣台北縣住址：台北縣瑞芳鎮上天里四腳亭埔路 30 號學歷：國立彰化師範大學工業教育學系電機工程組 (87 年 9 月~91 年 6 月) 國立交通大學電子研究所固態電子組 (92 年 9 月入學). 論文題目：. 1.8 伏金氧半低雜訊放大器應用於超寬頻 3.1-10.6GHZ 無線接收端 (A 1.8 -V CMOS LNA applied for Ultra-Wideband 3.1 to 10.6GHZ Wireless Receivers). 50.

(59)