Device Performance

Field emission characteristics of devices were measured with a triode-type configuration in a high-vacuum chamber with the pressure of 5×10^-6 Torr. A glass substrate coated with indium tin oxide (ITO) and P22 phosphor (ZnS: Cu, Al) was used as the anode plate, and the gap between the cathode and the anode plates was set to be 550 µm. Gate voltages up to 80 V were applied at intervals of 1 V with a source measure unit (Keithley 237) for the verification of field emission characteristics while the cathode and anode were biased at 0 and 1000 V, respectively.

The field emission characteristics of devices with conventional and self-focusing gate structures illustrated as a curve of anode current (Ia) versus extraction gate voltage (Vg) is shown in Fig. 4.11, and the inset represents the corresponding Fowler-Nordheim (F-N) plot. The emission anode currents at the gate voltage of 80 V

for conventional and self-focusing device were of 7.82 and 6.64 mA, respectively.

The distances between CNTs and gate electrodes in both the two structures were designed in the same configuration, i.e., nearly 200 nm, which was the simulation parameter assigned in Figs. 4.2 and 4.5. Therefore, the higher emission current in conventional gate structure was conjectured due to its larger extraction gate area as compared with that in self-focusing one. Although the conventional structure had a higher emission current than the self-focusing one, there was no enormous difference between them.

The photo-luminescent images taken via CCD camera were shown in Fig. 4.12.

The fact that the photo-luminescent image for the self-focusing gate structure was a bit asymmetrical may come from some reasons, such as the misalignment of the gate electrodes in the y-axis direction with respect to the area of CNT emitters and the non-uniformity of CNTs. Because of the alignment error in photolithography process, an asymmetry of electron beam trajectory in the y-axis would take places and thus resulted in an asymmetric photo-luminescent image. In addition, as the morphology of CNTs in the emission region has non-uniformity issue, the electrons emitted from CNTs governed by the electric field would have different beam trajectories, and therefore the photo-luminescent images would be not symmetrical. Nevertheless, the spot sizes shown on the anode plate along the x-axis were qualitatively consistent with the simulation results, indicating that the self-focusing structure could alleviate the issue of beam divergence and had good functionality in controlling the electron beams as compared with the conventional structure.

4.4 Summary

The field emission devices with a novel self-focusing gate structure consisting of CNT emitters have been successfully fabricated to show a good controllability in the luminescent spot size as compared with those with conventional structure. The results of simulations and luminescent images clearly indicated that the self-focusing gate structure employing a pair of gate electrodes close to the emitters could produce an asymmetric emission area, and the emitted electrons traveling through the spacing between cathode and anode plates would give rise to an overlapping region on the anode plate. Because of the overlapping of electron beams, the luminescent spot sizes could be remarkably reduced to 232 µm in x direction as compared with 622 µm for the conventional gate structure which had a serious issue of beam divergence. As a result, the self-focusing gate structure manufactured with a simple process can produce well-focused electron beams for the application in FEDs.

Chapter 5

Fabrication and Emission Characteristics of Chromium Thin Film Edge Emitters

In this chapter, two simple techniques were proposed for creating sub-micron gaps in edge field emitters. A lateral field emitter was manufactured by thin-film deposition and wet etching processes. The spacing was determined by the lateral etching distance formed during etching stage. In addition, a novel quasi-planar thin-film field emitter was fabricated utilizing the similar idea, and the spacing between the emitter and collector could be well controlled via the thickness of Cr layers, which created sub-micron gap. The device performance could be improved via a forming process which resulted in an increased surface roughness of emitters, thus a higher field enhancement factor.

5.1 Introduction

Recently, there has been a great amount of interest in vacuum microelectronic (VME) devices due to their high tolerance to high temperature and high radiation environment than solid state devices. With the technological breakthroughs in the microfabrication technology and the successful use of field emitters as the source of electrons, VME devices could reap the benefits of both conventional vacuum and solid state devices, and overcome most of the drawbacks associated with the traditional vacuum tubes. In addition, they are particularly used for high speed and

high frequency applications due to their low capacitance features [5.1-5.3]. Two types of microelectronic devices have been proposed: vertical and lateral (planar) type.

Vertical type field emission devices have the difficult in incorporation with the collector electrode, and therefore require a series of complicated processing steps to form a cantilevered electrode [5.4]. In the contrary, lateral (planar) field emission devices have attracted considerable attention in vacuum microelectronics due to ease of fabrication, design versatility of electrode geometry, and precise control of spacing between electrodes. Besides, owing to the low operation voltage and simplicity in device structure, lateral field emission devices had attracted much attention for the application in field emission displays (FEDs) [5.5].

Since a small spacing between electrodes is required for the reduction in the operation voltage of lateral field emission devices, thereby a lower power consumption, there have been several methods developed to create the small gaps. A subtenth-micron emitter to anode spacing could be fabricated by using high resolution electron beam lithography (EBL) in combination with a lift-off process [5.6]. Gotoh et al. employed a focus ion beam (FIB) technique for the fabrication of lateral-type thin-film edge field emitters [5.7-5.8]. Lee et al. proposed a novel sub-micron gap fabrication method using chemical-mechanical polishing (CMP) to fabricate lateral field emission devices [5.9]. Additionally, the thin film stress generated during high-temperature annealing and cooling could form a nanometer scale silicon gap, which is dependent upon the width of pattern and annealing temperature [5.10].

However, a low throughput is generally limited for the fabrication processes via EBL and FIB techniques. A high-temperature oxidation process is necessary for the CMP and thin film stress techniques, and this also give rise to a high thermal budget. In 2005, Canon and Toshiba demonstrated a 36 inch field emission flat-panel display based on the technology of surface conduction electron emitters [5.11], whose

structure is similar to the lateral field emitters. A nano-scale gap was generated by a forming and activation processes treating on a fine particle film of PdO deposited between two Pt electrodes. The panel showed an amazing graphic image in high quality just like CRTs. However, the manufacturing method is not compatible with thin film deposition process, and thus the productivity is at issue.

In this chapter, the objective of the work was to fabricate a field emission diode which could operate at a low voltage and have a well-controlled sub-micron spacing between the emitter and collector without using complicated manufacturing processes and instruments. Moreover, a low temperature process was also necessary for the destination of being compatible with glass substrates. Two types of lateral field emitters slightly different in fabrication processes were proposed to investigate the field emission characteristics.

5.2 Planar Edge Field Emitter

5.2.1 Sample Fabrication and Analysis

The process flows for manufacturing the planar field emitters were illustrated in Fig. 5.1, which mainly involved the wet-etching and lift-off techniques. Fist, a N-type silicon wafer on which a oxide layer was deposited by PECVD was used as the substrate. A chromium thin film with the thickness of 100 nm was formed on the substrate via electron beam evaporation; followed by a photolithography technique, a wet-etching method was conducted to control the lateral etching distance via the Cr etching solution (CR7T). Then, a second Cr thin film was deposited and lift-off to form a collector electrode.

The morphologies of the samples were characterized by scanning electron microscopy

(SEM; Hitachi S-4700I) and by atomic force microscopy (AFM; Ve e c o D i m e n s i o n 5 0 0 0 ). The spacing between emitter and collector electrodes could be controlled by the duration of wet-etching, and the corresponding SEM images of submicron gaps were displayed in Fig. 5.2. A SEM micrograph in low magnification shown in Fig. 5.3 revealed the diode device whose emission area was defined to be 200 µm in length by photolithography.

5.2.2 Field Emission Characteristics

The field emission characteristics of planar emitters were characterized in the diode configuration, which was schematically illustrated in Fig. 5.4. Measurement was performed in a high vacuum chamber with a base pressure of 5×10^-6 Torr; the emitter electrode was biased at ground voltage and collector electrode was drove to positive voltage swing for examining the emission current. As shown in Fig. 5.5, the turn-on voltage, representing the operation voltage of collector required for emission current of 100 nA, was significantly dependent on the gap spacing, that is, turn-on voltage of 48, 62, and 126 V for gap spacing of 200, 300, and 500 nm, respectively.

Since the small spacing experienced a higher electric field across the electrodes at the same driving voltage, a low turn-on voltage was expected to induce the electrons emitted out from the emitters. On the other hand, as the spacing got larger, a higher turn-on voltage was necessary for achieving the same emission current. It was worth noted that the device constructed in this work showed a comparable characteristics as compared with the other work mentioned above. Instead of utilizing complex and high-temperature techniques, the method combining wet-etching and lift-off provided a potential process for creation of submicron gap in the manufacture of field emission devices.

5.3 Quasi-Planar Edge Field Emitters

5.3.1 Sample Fabrication and Analysis

Another process of thin film edge emitters was also proposed as following.

Figure 5.6 showed the schematic diagram of the fabrication procedure of a quasi-planar field emission diode. A first metallic thin film of chromium (Cr, 300 nm) and an insulated silicon oxide layer (500 nm) were sequentially deposited on a N-type silicon substrate by E-beam evaporation and plasma-enhanced chemical vapor deposition (PECVD), respectively (Fig. 5.6(a)). The thickness of Cr thin film was used to define and control the spacing or the gap distance between the emitters and collectors. After photolithography, the silicon oxide layer and the first Cr thin film were isotropically wet-etched so as to form an undercut (Fig. 5.6(b)). The lateral etching distance of the first Cr layer should be larger than that of silicon oxide, thus forming a micro-cavity of Cr layer under the overhang of silicon oxide. Then, a second Cr layer with the thickness of 100 nm was deposited for the formation of emitter and collector (Fig. 5.6(c)). Finally, a forming process was employed for treatment of the second Cr layer (Fig. 5.6(d)). During the forming process, samples loaded into a quartz tube were heated to a temperature of 550 and kept for 30 min ℃ in a gas mixture of H2 (100 sccm) and C2H4 (50 sccm).

The cross-sectional and top-view SEM images of a quasi-planar field emission diode were shown in Fig. 5.7. In order to precisely control the field emission area, the measured device had an emission edge of 200 µm in length via photolithography patterning (Fig. 5.7(b)). Figs. 5.8(a) and 5.8(b) were the SEM images showing the surface morphologies of Cr thin film before and after the forming process, respectively. It was obviously seen that the forming process would cause a larger

roughness in the surface of Cr layer, thus resulting in better field emission characteristics. The surface morphology images of AFM shown in the insets indicated that the mean roughness of Cr thin films without the forming process was as low as 2.11 nm (Rrms= 2.72 nm) compared with those with the forming process (4.5 nm, Rrms= 5.70 nm). The increased surface roughness was conjectured due to the formation of chromium carbides in surface by thermal reaction [5.12].

5.3.2 Field Emission Characteristics

Field emission characteristics of devices were measured with a diode-type configuration in a high vacuum chamber with a pressure below 5×10^-6 Torr., and the schematic diagram of measurement was shown in Fig. 5.9. Driving voltages (Vd) up to 20 V were applied to the collector at intervals of 1 V by a source measure unit (Keithley 237) for the verification of field emission characteristics while the emitter was biased at 0 V.

A plot of the emission current versus driving voltage was shown in Fig. 5.10.

The device treated with forming process showed better field emission characteristics than that without forming process. As mentioned above, the surface morphologies treated by forming process presented a larger roughness than those un-treated.

Additionally, it was suggested that a improved field emission property results from the increasing film roughness by the modification of the surface morphology [5.13-5.14]. An emission surface having rougher morphologies possessed a higher field enhancement factor and more emission sites than flat one, thereby showing a better field emission performance. The turn-on voltage (Vto) at the emission current of 100 nA for the device with forming process was estimated to be 12 V, and an emission current of 8 µA could be achieve as the driving voltage applied to 20 V, which was as good as previous works [5.15-5.16]. The corresponding Fowler-Nordeim (F-N) plot of

the formed device shown in Fig. 5.10(b) represented a straight line of a negative slope at the high electric field region, implying that the current was due to field emission tunneling. However, the plot was oblique and deviated from the linearity at low electric field. Although the nonlinearity of F-N plot was still at issue, it may be attributed to surface states or geometrical effects as similar to the carbon materials [5.17-5.19]. It was also conjectured by other work that the nonlinearity in the F-N plot may be induced by the transition from thermionic to field emission [5.20].

The spacing between emitter and collector could be adjusted by the thickness of the first and second Cr layers. Owning to the second layer in this study was fixed at a thickness of 100 nm, the traveling distance of the emission electrons would be controlled by the thickness of the first Cr layer. Fig. 5.11 showed the variation of turn-on voltages with respect to the thickness of the first Cr layers, i.e. the gap distance between emitter and collector. As the gap distance decreases, the turn-on voltage decreased.

5.4 Summary

Planar thin film edge emitters were fabricated by simple techniques using thin film deposition and wet-etching processes. By controlling the duration of etching time, the distances between emitters and collectors were well defined in submicron ranges.

Device performance showed a low turn on voltage of 48 V at emission current of 100 nA as the emitter-collector spacing was 200 nm. In addition, a novel structure of quasi-planar field emission diode formed of Cr thin film was also proposed. The distances between emitters and collectors were controlled by changes in thickness of 2^nd Cr layers. Devices treated with a forming process at the temperature of 550 ha℃ d rougher surface morphologies than those un-treated due to the formation of carbides, which could significantly improve the field emission property. With the 1^st Cr layer of

300 nm, the turn-on voltage for quasi-planar devices was reduced from 22 to 12 V owing to the incorporation of forming process. The quasi-planar field emission diode with the first Cr layer of 200, 300, and 400 nm showed a low turn-on voltage of 9, 12, and 17 V, respectively, at the current level of 100 nA. Moreover, the spacing between the emitter and collector could be adjustable via the thickness of the first and second Cr layers, which is a simple process for scalability in the field emission devices.

Chapter 6

Summary and Conclusions

For the application of flat panel displays, large-area and cost-effective manufacture processes are essential for the profits of manufacturers. Glasses, naturally containing silica as a main component, could provide sufficient mechanical strength for fabrication processes, and seems to be a good candidate for supporting substrates. However, the softening point of glasses is about 580℃, which limits the fabrication processes that should be carefully designed so as to eliminate the issues of bending or cracking. Moreover, in order to eliminate the cross-talk noises between different pixels and to simply the manufacturing of triode devices based on CNT emitters, a new structure of device configuration was desired. In this dissertation, therefore, low-temperature fabrication processes of CNTs and thin film edge field emission devices were investigated due to their potential in application of flat panel displays; meanwhile, a new field emission triode device with self-focusing gate structure was proposed for simplicity in fabrication and feasibility in scalability.

First, CNTs were synthesized at 550℃using multilayer catalysts composed of a tri-layer structure via the atmospheric-pressure thermal CVD system. The fact that CNTs could be deposited at low temperatures with the multilayer catalysts was ascribed to the aspect of nano-effect caused by the supporting layer and interlayers.

The surface morphologies of catalysts pretreated in H2 ambient showed a tendency in reduction of particle sizes as the Al supporting layer of optimal thickness (10 nm) was employed. Interlayers which held similar surface energy as that of catalytic metal (Co) could improve the dispersion of nanoparticles as well. From the viewpoint of CNT

growth, a supersaturated carbon nearby the surface of catalytic nanoparticles would give rise to an effective growth of nanotubes since an enhanced precipitation of carbon promoted the formation of graphite sheets. Therefore, interlayers whose formation heat of carbides was positive could cause a local overcooled region at the surface of catalytic particles during their transformation into carbide phases. The overcooled region would induce a super-saturation of carbon concentration at local area, and further enhance the precipitation of carbon atoms. It was noted that Ti and Cr both showed the potential candidates for interlayers because of the good morphologies and field emission characteristics of CNTs and that he thickness ratio of interlayer over catalytic metal (2 nm Co) was suggested to be 1~2 both for Cr and Ti.

CNTs grown at 550℃ with the multilayer catalysts exhibited a high emission current density of 18.24 and 28.60 mA/cm² for the samples employed with interlayers of Cr (30 nm) and Ti (30nm), respectively, as the electric field was applied at 6 V/µm.

Next, in order to improve the morphologies and emission performance of CNTs grown at low temperatures, the flow rates of reaction gases composing of C2H4, H2, and N2 were changed to investigate and determine the optimal synthesis condition, which were characterized to be 125, 10, and 1000 sccm, respectively. Nanotubes synthesized with optimal growth condition revealed a good field emission performance of an emission current density of 26.50 mA/cm² at the electric field of 6.25 V/µm, and it also showed a low ID/IG ratio in Raman Spectrum analysis, indicating a good quality in crystallinity. The temperature-dependent growth rate in the Arrhenius plot for the multilayer catalyst revealed an activation energy of 0.89 eV, which is lower than that required for the single-layer catalyst in thermal decomposition (1.54 eV). The fact that CNTs could be deposited at low temperatures with multilayer catalyst was ascribe to the combination of well-distributed small catalytic nanoparticles due to the Al supporting layer and the higher activity due to the

Ti co-catalyst layer. Since the nano-sized catalytic particles had large surface to volume ratios, the diffusion path of carbon atoms prior precipitation at particle surfaces was comparable in proportion to that inside particles. Therefore, the

Ti co-catalyst layer. Since the nano-sized catalytic particles had large surface to volume ratios, the diffusion path of carbon atoms prior precipitation at particle surfaces was comparable in proportion to that inside particles. Therefore, the