9 Cycle and Response Times of the S7-400
9.11 CBA response times
9.11 CBA response times
Definition of the Response Time
The response time is the time that it takes a value from the user program of a CPU to reach the user program of a second CPU. This assumes that no time is lost in the user program itself.
Response Time for Cyclic Interconnection
The response time of an interconnection in an S7-400 CPU is composed of the following portions:
● Processing time on the transmitting CPU
● The transmission frequency configured in SIMATIC iMap (fast, medium or slow)
● Processing time on the receiving CPU
You have specified a value for the transmission frequency suited to your plant during the configuration with SIMATIC iMap. Faster or slower response times can occur because the data transmission to the user program is performed asynchronously. Therefore, check the achievable response time during commissioning and change the configuration as required.
Measurements for Cyclic Interconnections in an Example Configuration
To be able to estimate the achievable CBA response time better, consider the following measurements.
The processing times on the transmitting CPU and the receiving CPU basically depend on the sum of the input and output interconnections and the amount of data on them. The following figure shows this relationship using two examples for transmitting 600 bytes and 9600 bytes to a varying number of interconnections:
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Cycle and Response Times of the S7-400 9.11 CBA response times
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Figure 9-11 Processing time for sending and receiving
You can estimate the CBA response time using the information in this figure and the time you have set for the transmission frequency.
The following applies:
CBA response times =
Processing time on the transmitting CPU* +
Cycle time based on the configured transmission frequency** + Processing time on the receiving CPU*
*) Add all input and output interconnections of the CPU to determine the processing time.
You can read the processing time from the diagram based on the determined number of interconnections and amount of data on them.
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Cycle and Response Times of the S7-400 9.11 CBA response times
**) The configured transmission frequency has a direct relationship to the actual cycle time in the network. For technical reasons, the cycle time is based on the square of the base cycle time of 1ms. The actual cycle time therefore corresponds to the next smaller square of the configure transmission frequency; the following relationships result from the specified values:
(transmission frequency <-> cycle time): 1<->1 | 2<->2 | 5<->4 | 10<->8 | 20<->16 | 50<->32
| 100<->64 | 200<->128 | 500<->256 | 1000<->512 Note
Using iMap as of V3.0 SP1
In iMap as of V3.0 SP1 there are only squares of the base cycle time of 1ms for cyclic interconnections. The preceding footnote **) then no longer applies.
Note on the Processing Times for Cyclic Interconnections
● The processing times are based on 32 remote partners. Few remote partners reduces the processing times by approx. 0.02 ms per partner.
● The processing times are based on byte interconnections (single bytes or arrays).
● The processing times are applicable for situations in which the same transmission frequency is configured for all cyclic interconnections. Increased transmission frequency can improve the performance.
● When acyclic interconnections with the maximum amount of data are simultaneously active, the response times of the cyclic interconnections increase by approx. 33%.
● The example measurements were performed with a CPU 416-3 PN/DP. With a CPU 414-3 PN/DP the processing times increase by up to approx. 20%.
Response Time for Acyclic Interconnections
The resulting response time depends on the configured sampling frequency and the number of cyclic interconnections that are simultaneously active. You can see three examples for the resulting response times in the following table.
Table 9- 11 Response time for acyclic interconnections
Configured sampling frequency Resulting response time without
cyclic interconnections Resulting response time with cyclic interconnections
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Cycle and Response Times of the S7-400 9.11 CBA response times
General Information about Achievable CBA Response Times
● The CBA response time increases if the CPU is performing additional tasks, such as programmed block communication or S7 connections.
● If you frequently call SFCs "PN_IN", "PN_OUT" or "PN_DP", you increase the CBA processing times and therefore increase CBA response time.
● A very small OB1 cycle increases the CBA response time when the PN interface is updated automatically (at the cycle control point).
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Technical specifications 10
10.1 Specifications of the CPU 412-1 (6ES7412-1XJ05-0AB0)
Data
CPU and firmware version
MLFB 6ES7412-1XJ05-0AB0
• Firmware version V 5.2
Associated programming package as of STEP 7 V 5.3 SP2 + hardware update See also Introduction (Page 11)
Memory Working memory
• Integrated 144 KB for code
144 KB for data Load memory
• Integrated 512 KB RAM
• Expandable FEPROM With memory card (FLASH) up to 64 MB
• Expandable RAM With memory card (RAM) up to 64 MB
Backup with battery Yes, all data
Typical processing times Processing times of
• Bit operations 75 ns
• Word operations 75 ns
• Fixed-point arithmetic 75 ns
• Floating-point arithmetic 225 ns
Timers/counters and their retentivity
S7 counters 2048
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Technical specifications
10.1 Specifications of the CPU 412-1 (6ES7412-1XJ05-0AB0)
IEC timers Yes
• Type SFB
Data areas and their retentivity Total retentive data area (including memory
markers, timers, counters) Total work and load memory (with backup battery)
Bit memory 4 KB
• Retentivity programmable From MB 0 to MB 4095
• Preset retentive address areas From MB 0 to MB 15
Clock flag bits 8 (1 flag byte)
Data blocks Maximum 1500 (DB 0 reserved)
Band of numbers 1 - 16000
• Size Maximum 64 KB
Local data (programmable) Maximum 8 KB
• Preset 4 KB
Blocks
OBs See Instruction List
• Size Maximum 64 KB
SDBs Maximum 2048
Address areas (I/O)
Total I/O address area 4 KB / 4 KB
including diagnostics addresses, addresses for I/O interface modules, etc
Distributed of this
• MPI/DP interface 2 KB / 2 KB
Process image 4 KB/4 KB (programmable)
• Preset 128 bytes / 128 bytes
• Number of process image partitions Maximum 15
• Consistent data Maximum 244 bytes
Digital channels Maximum 32768 / maximum 32768
• Central of this Maximum 32768 / maximum 32768
Analog channels Maximum 2048 / maximum 2048
• Central of this Maximum 2048 / maximum 2048
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Technical specifications 10.1 Specifications of the CPU 412-1 (6ES7412-1XJ05-0AB0)
Configuration Central racks/expansion units Maximum 1/21
Multicomputing Maximum 4 CPUs with UR1 or UR2
Maximum of 2 CPUs with CR3 Number of plug-in IMs (total) Maximum 6
• IM 460 Maximum 6
• IM 463-2 Maximum 4
Number of DP masters
• Integrated 1
• Via IM 467 Maximum 4
• Via CP 443-5 Extended Maximum 10
IM 467 cannot be used with the CP 443-5 Extended
IM 467 cannot be used together with the CP 443-1 EX4x in PN IO mode Number of PN IO controllers
• Via CP 443-1 in PN IO mode Maximum 4 in central rack, see manual for CP 443-1, no combined operation of CP 443-1 EX40 and CP443-1EX41/EX20/GX20
Number of plug-in S5 modules via adapter
casing (in the central rack) Maximum 6 Operable function modules and communication
processors
• FM Limited by the number of slots and the number of
connections
• CP 440 Limited by the number of slots
• CP 441 Limited by the number of connections
• PROFIBUS and Ethernet CPs including
CP 443-5 Extended and IM 467 Maximum 14
No more than 10 of which may be CPs or IMs as DP master, up to 4 PN IO controllers
Time of day
Clock Yes
• Buffered Yes
• Resolution 1 ms
• Accuracy after POWER OFF Maximum deviation per day 1.7 s
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Technical specifications
10.1 Specifications of the CPU 412-1 (6ES7412-1XJ05-0AB0)
Time difference in the system with
synchronization via MPI Maximum 200 ms
S7 message functions Number of stations that can log on for message
functions (e.g. WIN CC or SIMATIC OP) Maximum 8 with ALARM_8 or ALARM_P (WinCC); up to 31 with ALARM_S or ALARM_D (OPs)
Symbol-related messages Yes
• Number of messages Total
100 ms interval 500 ms interval 1000 ms interval
Maximum 512 None
Maximum 256 Maximum 256
• Number of auxiliary values per message With 100 ms interval
With 500, 1000 ms interval None
1
Block-related messages Yes
• Simultaneously active ALARM_S/SQ blocks
and ALARM_D/DQ blocks Maximum 250
ALARM_8 blocks Yes
• Number of communication jobs for ALARM_8 blocks and blocks for S7 communication (programmable)
Maximum 300
• Preset 150
Process control messages Yes
Number of archives that can log on
simultaneously (SFB 37 AR_SEND) 4
Test and startup functions
Status/modify variable Yes, maximum 16 variable tables
• Variable Inputs/outputs, memory markers, DB, distributed
inputs/outputs, timers, counters
• Number of variables Maximum 70
Force Yes
• Variable Inputs/outputs, memory markers, distributed
inputs/outputs
• Number of variables Maximum 64
Status block Yes, maximum 2 blocks at the same time
Single-step Yes
Number of breakpoints 4
Diagnostic buffer Yes
• Number of entries Maximum 200 (programmable)
• Preset 120
Cyclic interrupts
Value range 500 µs to 60000 ms
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Technical specifications 10.1 Specifications of the CPU 412-1 (6ES7412-1XJ05-0AB0)
Communication
PG/OP communication Yes
Number of connectable OPs 31
Number of connection resources for S7
connections via all interfaces and CPs 32, with one each of those reserved for programming device and OP
Global data communication Yes
• Number of GD circuits Maximum 8
• Number of GD packets Sender
Receiver Maximum 8
Maximum 16
• Size of GD packets
Consistent of this Maximum 54 bytes
1 variable
S7 basic communication Yes
• MPI Mode Via SFC X_SEND, X_RCV, X_GET and X_PUT
• DP Master Mode Via SFC I_GET and I_PUT
• User data per job
Consistent of this Maximum 76 bytes
1 variable
S7 communication Yes
• User data per job
Consistent of this Maximum 64 KB
1 variable (462 bytes)
S5-compatible communication Via FC AG_SEND and AG_RECV, max. via 10 CP 443-1 or 443-5)
• User data per job
Consistent of this Maximum 8 KB
240 bytes
• Number of simultaneous
AG-SEND/AG-RECV jobs per CPU, maximum 24/24
Standard communication (FMS) Yes (via CP and loadable FBs)
Open IE communication ISO on TCP via CP 443-1 and downloadable FBs
• Maximum data length 1452 bytes
Interfaces 1st interface
Type of interface Integrated
Features RS 485 / PROFIBUS
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Technical specifications
10.1 Specifications of the CPU 412-1 (6ES7412-1XJ05-0AB0)
1st interface MPI mode Services
PG/OP communication Routing
Global data communication S7 basic communication S7 communication Time synchronization
Yes Yes Yes Yes Yes Yes
Transmission rates Up to 12 Mbps
1st interface DP master mode Services
PG/OP communication Routing
S7 basic communication S7 communication Constant cycle SYNC/FREEZE
Activate/deactivate DP slaves Time synchronization
Direct data communication (internetwork traffic) Yes Yes Yes Yes Yes Yes Yes Yes Yes
Transmission rates Up to 12 Mbps
Number of DP slaves Maximum 32
Number of slots per interface Maximum 544
Address area Maximum 2 KB inputs / 2 KB outputs
User data per DP slave Maximum 244 bytes
Maximum 244 bytes I and Maximum 244 bytes O, Maximum 244 slots Maximum 128 bytes per slot Note:
• The total sum of the input bytes across all slots may not exceed 244.
• The total sum of the output bytes across all slots may not exceed 244.
• The address range of the interface (maximum 2 KB inputs / 2 KB outputs) must not be exceeded in total across all 32 slaves.
1st interface DP slave mode Service
GSD file: http://support.automation.siemens.com/WW/view/en/113652
Transmission rate Up to 12 Mbps
Transfer memory Virtual slots
User data per address area Consistent of this
244 bytes inputs / 244 bytes outputs Maximum 32
Maximum 32 bytes 32 bytes
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Technical specifications 10.1 Specifications of the CPU 412-1 (6ES7412-1XJ05-0AB0)
Programming
Programming language LAD, FBD, STL, SCL, S7 GRAPH, S7 HiGraph
Instruction set See Instruction List
Nesting levels 7
System functions (SFC) See Instruction List Number of simultaneously active SFCs per
segment
• SFC 11 "DPSYC_FR" 2
• SFC 12 "D_ACT_DP" 8
• SFC 59 "RD_REC" 8
• SFC 58 "WR_REC" 8
• SFC 55 "WR_PARM" 8
• SFC 57 "PARM_MOD" 1
• SFC 56 "WR_DPARM" 2
• SFC 13 "DPNRM_DG" 8
• SFC 51 "RDSYSST" 1 ... 8
• SFC 103 "DP_TOPOL" 1
System function blocks (SFB) See Instruction List Number of simultaneously active SFBs
• SFB 52 "RDREC" 8
• SFB 53 "WRREC" 8
User program protection Password protection Access to consistent data in the process image Yes
Isochronous mode
User data per isochronous slave Maximum 244 bytes Maximum number of bytes and slaves in a
process image partition The following must apply:
Number of bytes/100 + number of slaves < 16
Constant bus cycle time Yes
Shortest clock pulse 1.5 ms
0.5 ms without use of SFC 126, 127
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Technical specifications
10.1 Specifications of the CPU 412-1 (6ES7412-1XJ05-0AB0)
Voltages, currents Current consumption from the S7-400 bus (5
VDC) Typically 0.5 A
Maximum 0.6 A Current consumption from S7-400 bus (24 VDC)
The CPU does not consume any current at 24 V, it only makes this voltage available at the MPI/DP interface.
Total current consumption of the components connected to the MPI/DP interfaces, with a maximum of 150 mA per interface
Backup current Typically 125 µA (up to 40° C)
Maximum 550 µA
Maximum backup time See Module Specifications reference manual, Section 3.3.
Supply of external backup voltage to CPU 5 to 15 VDC
Power loss Typically 2.5 W
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