8 Memory concept
8.1 Overview of the memory concept of S7-400 CPUs
Organization of Memory Areas
The memory of the S7 CPUs can be divided into the following areas:
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Memory concept
8.1 Overview of the memory concept of S7-400 CPUs
Memory Types in S7-400 CPUs
● Load memory for the project data, e.g. blocks, configuration and parameter settings.
● Work memory for the runtime-relevant blocks (logic blocks and data blocks).
● System memory (RAM) contains the memory elements that each CPU makes available to the user program, such as bit memory, timers and counters. System memory also
contains the block stack
● System memory of the CPU also makes temporary memory available (local data stack, diagnostic buffer and communication resources) that is assigned to the program for the temporary data of a called block. These data is only valid as long as the block is active.
By changing the default values for the process image, local data, diagnostic buffer and communication resources (see object properties of the CPU in HW Config), you can influence the work memory available to the runtime-relevant blocks.
NOTICE
Please note the following if you expand the process image of a CPU. Reconfigure modules whose addresses have to be over the highest address of the process image so that the new addresses are still over the highest address of the expanded process image. This applies, in particular, to IP and WF modules that you operate in the S5 adapter casing in an S7-400.
Important note for CPUs after the parameter settings for the allocation of RAM have been changed If you change the work memory allocation by modifying parameters, this work memory is reorganized when you load system data into the CPU. The result of this is that data blocks that were created with SFC are deleted, and the remaining data blocks are assigned initial values from the load memory.
The usable size of the working memory for logic or data blocks is changed when loading the system data if you change the following parameters:
● Size of the process image (byte-oriented; in the "Cycle/Clock Memory" tab)
● Communication resources (S7-400 only; "Memory" tab)
● Size of the diagnostic buffer ("Diagnostics/Clock" tab)
● Number of local data for all priority classes ("Memory" tab)
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Memory concept 8.1 Overview of the memory concept of S7-400 CPUs
Basis for Calculating the Required Working Memory
To ensure that you do not exceed the available amount of working memory on the CPU, you must take into consideration the following memory requirements when assigning parameters:
Table 8- 1 Memory requirements
Parameters Required working memory In code/data memory
Size of the process image (inputs) 12 bytes per byte in the process input image Code memory Size of the process image (outputs) 12 bytes per byte in the process output image Code memory Communication resources
(communication jobs) 72 bytes per communication job Code memory Size of the diagnostic buffer 32 bytes per entry in the diagnostic buffer Code memory Quantity of local data 1 byte per byte of local data Data memory
Flexible Memory Capacity
● Work memory:
The capacity of the work memory is determined by selecting the appropriate CPU from the graded range of CPUs.
● Load memory:
The integrated load memory is sufficient for small and medium-sized programs.
The load memory can be increased for larger programs by inserting the RAM memory card.
Flash memory cards are also available to ensure that programs are retained in the event of a power failure even without a backup battery. Flash memory cards (8 MB or more) are also suitable for sending and carrying out operating system updates.
Backup
● The backup battery provides backup power for the integrated and external part of the load memory, the data section of the working memory and the code section.
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Memory concept
8.1 Overview of the memory concept of S7-400 CPUs
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Cycle and Response Times of the S7-400 9
9.1 Cycle time
Definition of the Cycle Time
The cycle time represents the time that an operating system needs to execute a program, that is, one OB 1 cycle, including all program sections and system activities interrupting this cycle.
This time is monitored.
Time-Sharing Model
Cyclic program scanning, and thus also processing of the user program, is performed in time slices. So that you can better appreciate these processes, we will assume in the following that each time slice is exactly 1 ms long.
Process Image
The process signals are read or written prior to program scanning so that a consistent image of the process signals is available to the CPU for the duration of cyclic program scanning.
Then the CPU does not directly access the signal modules during program scanning when the address area "inputs" (I) and "outputs" (O) are addressed, but addresses instead the internal memory area of the CPU on which the image of the inputs and outputs is located.
The Cyclic Program Scanning Process
The following table and figure illustrate the phases of cyclic program scanning.
Table 9- 1 Cyclic program processing
Step Process
1 The operating system starts the scan cycle monitoring time.
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Cycle and Response Times of the S7-400 9.1 Cycle time
Parts of the Cycle Time
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Cycle and Response Times of the S7-400 9.2 Cycle Time Calculation
9.2 Cycle Time Calculation
Increasing the Cycle Time
Basically, you should note that the cycle time of a user program is increased by the following:
● Time-driven interrupt processing
● Hardware interrupt processing
● Diagnostics and error handling
● Communications via the MPI, PROFINET interface and CPs connected automation-system internally
(for example, Ethernet, PROFIBUS DP); included in the communication load
● Special functions such as control and monitoring of tags or block status
● Transfer and clearance of blocks, compression of the user program memory
● Internal memory test
Influencing factors
The following table indicates the factors that influence the cycle time.
Table 9- 2 Factors that Influence the Cycle Time
Factors Remarks
Transfer time for the process-image output table (PIQ) and the process-image input table (PII)
... See table 9.3 "Portions of the process image transfer time"
User program
execution time ... is calculated from the execution times of the different instructions, see S7-400 Instruction List.
Operating system scan time at
the scan cycle checkpoint ... See table 9.4 "Operating system scan time at the scan cycle checkpoint"
Increase in the cycle time through
communications You set the maximum permissible cycle load expected for communication in % in STEP 7, see manual Programming with STEP 7.
Impact of interrupts on the cycle
time Interrupt can interrupt the user program at any time.
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Cycle and Response Times of the S7-400 9.2 Cycle Time Calculation
Process image update
The table below shows the CPU times for process image updating (process image transfer time). The times listed in the table are "ideal values" that may be increased by the
occurrence of interrupts and by CPU communications.
The transfer time for process image updating is calculated as follows C + portion in the central rack (from row A in the following table)
+ portion in the expansion rack with local connection (from row B) + portion in the expansion rack with remote connection (from row C) + portion via integrated DP interface (from row D)
+ portion of consistent data via integrated DP interface (from row E1) + portion of consistent data via external DP interface (from row E2) + portion via integrated PN/IO interface (from row F1)
+ portion via external PN/IO interface (from row F2)
__________________________________________________________________
= Transfer time for the process image update
The tables below show the individual portions of the transfer time process image updating (process image transfer time). The times listed in the table are "ideal values" that may be increased by the occurrence of interrupts and by CPU communications.
Table 9- 3 Portions of the process image transfer time
Portions CPU 412 CPU 414 CPU 416 CPU 417
n = number of bytes in the process image
C Base load 14 µs 7 µs 5 µs 3 µs
O In the central rack *) n * 1.9 µs n * 1.8 µs n * 1.75 µs n * 1.7 µs B In the expansion rack with local connection *) n * 5.6 µs n * 5.5 µs n * 5.4 µs n * 5.3 µs C In the expansion rack with remote connection *) **)
Reading
E1 Consistent data in the process image for the integrated
DP interface n * 0.8 µs n * 0.45 µs n * 0.3 µs n * 0.2 µs
E2 Consistent data in the process image for the external
DP interface (CP 443-5 extended) n * 2.0 µs n * 2.0 µs n * 2.0 µs n * 1.8 µs F1 In the PN/IO area for the integrated interface - n * 5.6 µs n * 5.6 µs -
F2 In the PN/IO area for the external interface
CP 443-1 EX 41 n * 3.4 µs n * 3.1 µs n * 2.8 µs n * 2.6 µs
*In the case of I/O modules that are plugged into the central rack or an expansion rack, the specified value contains the runtime of the I/O module
**Measured with the IM 460-3 and IM 461-3 with a connection length of 100 m
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Cycle and Response Times of the S7-400 9.2 Cycle Time Calculation
Operating System Scan Time at the Scan Cycle Checkpoint
The table below lists the operating system scan times at the scan cycle checkpoint of the CPUs.
Table 9- 4 Operating System Scan Time at the Scan Cycle Checkpoint
Process CPU 412 CPU 414 CPU 416 CPU 417
Scan cycle control at the SCC 213 µs to 340 µs Ø 231 µs
160 µs to 239 µs Ø 168 µs
104 µs to 163 µs Ø 109 µs
49 µs to 87 µs Ø 52 µs
Increase in cycle time by nesting interrupts
Table 9- 5 Increase in cycle time by nesting interrupts
CPU Hardware
interrupt Diagnostic
interrupt Time-of-day
Interrupt Time-delay
interrupt Cyclic interrupt Programming / PI/O access error
CPU 412-1/-2 529 µs 524 µs 471 µs 325 µs 383 µs 136 µs / 136 µs
CPU 414-2/-3 314 µs 308 µs 237 µs 217 µs 210 µs 84 µs / 84 µs
CPU 416-2/-3 213 µs 232 µs 139 µs 135 µs 141 µs 55 µs / 56 µs
CPU 417-4 150 µs 156 µs 96 µs 75 µs 92 µs 32 µs / 32 µs
You will have to add the program execution time at the interrupt level to this increase.
If several interrupts are nested, their times must be added together.
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Cycle and Response Times of the S7-400 9.3 Different cycle times
9.3 Different cycle times
Fundamentals
The length of the cycle time (Tcyc) is not identical in each cycle. The following figure shows different cycle times, Tcyc1 and Tcyc2. Tcyc2 is longer than Tcyc1, because the cyclically scanned OB 1 is interrupted by a time-of-day interrupt OB (here, OB10).
OB10
Current cycle Next cycle Next cycle but one
Figure 9-2 Different cycle times
Fluctuation of the block processing time (e.g. OB 1) may also be a factor causing cycle time fluctuation, due to:
● Conditional commands
● Conditional block calls
● Different program paths,
● Loops, etc.
Maximum Cycle Time
You can modify the default maximum cycle time in STEP 7 (cycle monitoring time). When this time has expired, OB 80 is called. In OB 80 you can specify how the CPU is to react to time errors. If you do not retrigger the cycle time with SFC43, OB 80 doubles the cycle time at the first call. In this case, the CPU goes to STOP at the second call of OB 80.
If there is no OB 80 in the CPU memory, the CPU goes to STOP.
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Cycle and Response Times of the S7-400 9.3 Different cycle times
Minimum Cycle Time
You can set a minimum cycle time for a CPU in STEP 7. This is appropriate in the following cases:
● you want the intervals of time between the start of program scanning of OB1 (free cycle) to be roughly of the same length.
● updating of the process images would be performed unnecessarily often with too short a cycle time.
● You want to process a program with the OB 90 in the background.
OB10
Current cycle Next cycle
Reserve
Tmin = the adjustable minimum cycle time Tmax = the adjustable maximum cycle time Tcyc = the cycle time
Twait = the difference between Tmin and the actual cycle time; in this time,
any interrupts that occur, the background OB and the SCC tasks can be processed.
PCI = priority class
. . .
Figure 9-3 Minimum cycle time
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Cycle and Response Times of the S7-400 9.4 Communication Load
9.4 Communication Load
Overview
The CPU operating system continually makes available to communications the percentage you configured for the overall CPU processing performance (time sharing). Processing performance not required for communication is made available to other processes.
In the hardware configuration, you can set the load due to communications between 5%
and 50%. By default, the value is set to 20%.
This percentage should be regarded as an average value, in other words, the
communications component can be considerably greater than 20% in a time slice. On the other hand, the communications component in the next time slice is only a few or zero percent.
This fact is also expressed by the following equation:
100
= x
Actual
cycle time Cycle time
Round up the result to the next whole number !
100 - "configured communication load in %"
Figure 9-4 Equation: Influence of communication load
Note
Real and configured communication load
The configured communication load alone has no effect on the cycle time. The cycle time is only influenced by the communication load actually occurring. In other words, when a communication load of 50% is configured and a communication load of 10% occurs in a cycle, the cycle time is not doubled, it only increases by a factor of 1.1.
Data consistency
The user program is interrupted for communications processing. The interrupt can be
executed after any instruction. These communication jobs can modify the program data. This means that the data consistency cannot be guaranteed for the duration of several accesses.
The section Consistent Data provides more information about how to ensure consistency when there is more than one command.
Time slice (1 ms)
Operating system between 5 and 50%
Figure 9-5 Breakdown of a time slice
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Cycle and Response Times of the S7-400 9.4 Communication Load
Of the part remaining, the operating system of the S7-400 requires only a negligibly small amount for internal tasks.
Example: 20% communication load
You have configured a communication load of 20% in the hardware configuration.
The calculated cycle time is 10 ms.
A 20% communication load means that, on average, 200 μs and 800 μs of the time slice remain for communications and the user program, respectively. The CPU therefore requires 10 ms / 800 μs = 13 time slices to process one cycle. This means that the actual cycle time is 13 times a 1 ms time slice = 13 ms, if the CPU fully utilizes the configured communication load.
This means that 20% communications do not increase the cycle linearly by 2 ms but by 3 ms.
Example: 50 % communication load
You have configured a communication load of 50% in the hardware configuration.
The calculated cycle time is 10 ms.
This means that 500 μs of each time slice remain for the cycle. The CPU therefore requires 10 ms / 500 μs = 20 time slices to process one cycle. This means that the actual cycle time is 20 ms if the CPU fully utilizes the configured communication load.
A 50% communication load means that 500 μs of the time slice remain for communication and 500 μs for the user program. The CPU therefore requires 10 ms / 500 µs = 20 time slices to process one cycle. This means that the actual cycle time is 20 times a 1 ms time slice = 20 ms, if the CPU fully utilizes the configured communication load.
This means that 50% communications do not increase the cycle linearly by 5 ms but by 10 ms.
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Cycle and Response Times of the S7-400 9.4 Communication Load
Dependency of the Actual Cycle Time on the Communication load
The following figure describes the non-linear dependency of the actual cycle time on the communication load. This example uses a cycle time of 10 ms.
0 % 10 % 20 % 30 % 40 % 50 % 60 %
10 ms 20 ms 25 ms
15 ms
5 ms 30 ms
5 % Cycle time
You can set the communication load in this range
Communication load
Figure 9-6 Dependency of the Cycle Time on the Communication load
Further Effect on the Actual Cycle Time
Due to the increase in the cycle time as a result of the communications component, even more asynchronous events occur, from a statistical point of view, within an OB 1 cycle than, say, interrupts. This also increases the OB 1 cycle. This extension depends on the number of events that occur per OB 1 cycle and the time required to process these events.
Notes
● Check the effects of a change of the value for the parameter "Cycle load due to communications" in system operation.
● The communication load must be taken into account when you set the maximum cycle time, since time errors will occur if it is not.
Recommendations
● If possible, apply the default value.
● Use a larger value only if the CPU is being used primarily for communication purposes and the user program is non-time-critical. In all other cases select a smaller value.
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Cycle and Response Times of the S7-400 9.5 Reaction Time
9.5 Reaction Time
Definition of the response time
The response time is the time from an input signal being detected to changing an output signal linked to it.
Variation
The actual response time is somewhere between a shortest and a longest response time.
For configuring your system, you must always reckon with the longest response time.
The shortest and longest response times are analyzed below so that you can gain an impression of the variation of the response time.
Factors
The response time depends on the cycle time and on the following factors:
● Delay in the inputs and outputs
● Additional DP cycle times on the PROFIBUS DP network
● Execution of the user program
Delay in the inputs and outputs
Depending on the module, you must heed the following time delays:
• For digital inputs: The input delay time
• For digital inputs with
interrupt capability: The input delay time +
module-internal preparation time
• For digital outputs Negligible delay times
• For relay outputs: Typical delay times of 10 ms to 20 ms.
The delay of the relay outputs depends, among other things, on the temperature and the voltage.
• For analog inputs: Analog input cycle time
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Cycle and Response Times of the S7-400 9.5 Reaction Time
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Figure 9-7 DP cycle times on the PROFIBUS DP network
With multi-master operation on a PROFIBUS DP network, you must make allowances for the DP cycle time at each master. That is, you will have to calculate the times for each master separately and then add up the results.
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