CFC LDO Regulator Structure

In the schematic shown in Fig. 49, the basic structure of this LDO regulator consists of three gain stage. The first stage is a differential to single out high gain stage which consists of M1~M6. The second gain stage consists of M7~M12 and RB. The transistor M7~M10 forms a wideband stage to create a ground reference form the compensation capacitor. And transistor M10~M12 and RB forms a common source stage with resistive load RB to achieve high PSR performance. The third gain stage is common source power PMOS stage. The feedback resistors RF1,2 form the shunt feedback effect to regulate the output voltage.

Fig. 49. Circuit schematic of CFC LDO regulator.

The dominant pole compensation capacitor is connected a ground reference, output of first stage, to the output to prevent noise directly pass to the output. The propose compensation network, Ca and Rz, is shown in dotted line in Fig. 49. The compensation capacitor Ca is connected to a ground reference to maintain high PSR performance. The dynamic resistor Rz acts dynamic zero compensation (DZC) is form by a PMOS operated in triode region controlled by the sensing network.

In order to achieve faster transient response, the unit gain bandwidth is set about near 1MHz. The compensation capacitor is usually in several pico-Farad. As shown in equation (77), the transconductance gm1 of input pair is set about 30 µS.

1 transconductance gm2 is set about 1 mS to have faster slewing.

The DC gain is about 95dB according to equation (78).

1 2 3

The nature frequency ωo according to equation (79) is about 4.5 MHz.

2 3 parameters of LDO under load current 50µA are listed in TABLE IV.

TABLE IV 61.3° respectively. The dominant pole is located at low frequency 19Hz. The nature frequency ωo is 4.5 MHz, and then the unit gain frequency is about 890 kHz. The first non-dominant pole is located at 1.8MHz to maintain the phase margin about 60°. The quality factor Q is 5.85 with nature frequency ω_o 4.5 MHz which has little effect on stability.

TABLE V sensing MOS MSEN is set to 1000, i.e. the current consumption is 100 µA as load is 100 mA.

The sensing resistor is designed to 2 kΩ to maintain the phase margin about 60° under the heaviest load 100 mA.

As mentioned before, the poles and zero locations are varied with load conditions. The poles and zero locations under different load condition are shown in TABLE VI. As load increased, the dominant pole is moved to higher frequency. However, the first non-dominant

pole is moved to lower frequency to degenerate the phase margin. But the dynamic zero compensation network generates a zero which is decreased as load increased. Therefore, the phase margin can be maintained near 60 degree. The nature frequency is increased as load increased, while the quality factor in decreased. And the complex poles will be become two separated poles under load current several mili-amp. The gain magnitude of proposed is decreased as load increased, and the unit gain frequency is near constant unless the heavy load condition with power MOS operated in linear region.

TABLE VI

ACPARAMETERS OF CFCCAPACITOR-FREE LDO UNDER DIFFERENT LOAD.

Load P-3dB P1st-non ZDZC ωo Q Avo UGF PM

50 µA 19 Hz 1.8 MHz 11.4 MHz 4.5 MHz 5.85 94.1dB 890kHz 61.3 500 µA 29 Hz 1.7 MHz 11.3 MHz 12.3MHz 5.00 90.4dB 855kHz 61.4 1 mA 34 Hz 1.7 MHz 11.3 MHz 16.0MHz 3.27 89.1dB 855kHz 63.7 10 mA 70 Hz 1.6 MHz 11.1 MHz -- -- 82.6dB 852kHz 63.6 50 mA 422 Hz 1.3 MHz 9.1 MHz -- -- 66.3dB 750kHz 58.6 100 mA 1 kHz 560 kHz 1.1 MHz -- -- 57.2dB 560kHz 58.5

↗ ↘ ↘ ↗ ↘ ↘

× ×

Fig. 50. Loop responses of CFC capacitor-free LDO under different load conditions.

The frequency response under different load current is shown in Fig. 50. The magnitude rolls off with -20dB/dec after the dominant pole and with -40dB/dec above the first non-dominant pole. The unit gain frequency and phase margin always keeps in 850 kHz and 60 degree respectively.

Compared with proposed LDO with and without compensation, the quality factor Q has been decreased greatly and occurs at lower magnitude as shown in Fig. 51. The pole locations without proposed compensation are located right-half-plane under load current 50µA and 100µA. Although the poles are located left-half-plane under load current 500µA, the quality factor is too large to make the system unstable. With proposed compensation, right-half-plane poles are converted to left-half-plane poles with low quality factor Q. The system is remained stable even with ultra light load current.

The PSR performance of proposed LDO is shown in Fig. 52. The DC PSR is -92.5dB and -66.6dB under load current 1mA and 100mA respectively. The PSR at 1MHz is -28dB and -10dB under load current 1mA and 100mA respectively.

Fig. 51. Loop responses with and without CFC technique.

The PSR performance with different compensation technique under load current 1mA is shown in Fig. 53. It shows that the high PSR characteristic is maintained even the CFC technique is used. If the Q-reduction technique is used, the PSR bandwidth is greatly reduced.

If the system needs an off-chip capacitor to have better transient response, the ESR is required to compensate the output low frequency pole. The frequency response with off-chip capacitor 10µF and ESR 1Ω under different load current is shown in Fig. 54.

Fig. 52. PSR performance of CFC capacitor-free LDO regulator.

Fig. 53. PSR performance with different compensation technique.

According to the theorem described in Chapter 3.2.2, the ESR zero is used to compensate the first non-dominant pole. Since the first non-dominant pole moves faster than dominant pole, the worse case stability occurs at no load condition. But the second non-dominant pole will move to lower frequency when the power MOS is operated from saturation region to linear region. The stability is degenerated at heavy load condition. So the ESR zero must maintain the stability in no load and heavy load conditions.

TABLE VII

Fig. 54. Loop responses under different load conditions with off-chip capacitor.