Chapter 4 Results and Discussions
4.4 Channel and Contact Resistance
In the previous section, OTFTs with different grain sizes were fabricate by controlling the substrate temperature to investigate the relationship between the grain size (boundary) and the carrier mobility.
In this section, we will analyze the electrical characteristics by the transfer line method to extract the minimum effective contact resistance, bulk resistance, and channel resistance, respectively. Thus, we will have more insight into the real situation that how the mobility improves by varying deposition temperature in these three parts.
4.4-1 Transfer Line Method
[33] [34]-40 0 40 80 120 160
0.0 4.0x10
58.0x10
51.2x10
61.6x10
62.0x10
6Channel Length (
μm)
Total Resistance (Ω)
VG=-60V VG=-45V VG=-30V Rc=1.37*105
Lo
Figure 4. 15 Total resistance as a function of channel length at various gate voltages.
The inset shows a simplified equivalent OTFT circuit where the conducting path is divided into three parts of resistance, (RcS+ RcD), (RbS+ RbD), Rch.
Figure 4. 15 presents the transfer line method for resistance extraction. In the linear regime, the total resistance (Rtotal) can be expressed as:
p
where . The channel resistance per μm can be extracted by the slope. On the other hand, the parasitic resistance (R
D y-axis intercept of the extrapolated linear fit of Rtotal versus L at various gate voltages.
All fitted lines meet at an intersection point which is the minimum effective contact resistance (RcS+ RcD) at x=-L0. Consequently, the bulk resistance (RbS+ RbD) can be obtained by the difference between Rp and (RcS+ RcD).
4.4-2 The Resistance Extraction from HMDS-Treated Device
0 40 80 120 160
To tal Resi stance (
Ω)
17oC @VG= -30V50oC 70oC
Channel Length (
μm)
Figure 4. 16 Total resistance as a function of channel length at various deposition temperatures which are extracted from the electrical characteristics of HMDS-treated device.
Channel Resistance
From the change of the slope, it is inferred that the channel resistance per μm reduces with increasing deposition temperature (Figure 4. 16). From the AFM images (Figure 4. 17), less grain boundary density for the device made at higher temperature was observed. Therefore, with the larger the grains, the channel resistance is lower.
Table 4. 2 The parameters of HMDS-treated device obtained under VG=-30V.
Substrate
*The value of Lo/L exhibits the ratio of bulk resistance to channel resistance (90 μm).
**Assume Cassie model is proper to apply in the pentacene surface [35].
Parasitic Resistance
From the y-axis intercept, it is also found that the parasitic resistance reduces with increasing deposition temperature, too. It is quite interesting to see the origins of the grain size effects on the Rp. From the method described above, we can separate the parasitic resistance into two parts, minimum effective contact resistance (RcS + RcD) and bulk resistance (RbS + RbD) as shown in Table 4. 2. The results are described as the following sections.
Minimum Effective Contact Resistance
Table 4. 2 shows that the contact resistance (RCS+RCD) reduced with temperature.
Assuming the resistance is inverse-proportional to the surface area, the contact surface should be confirmed. Since the surface area cannot deduced directly from the grain
size, Matlab (Program2 in the appendix) was used to calculate the surface area from the AFM images. The result indicates that the contact surface area of the device made at 20oC is about two-fold of that made at 70oC, suggesting a higher specific contact resistance for the device made at 20oC. Further, from the measurement of contact angle, different values were obtained for different devices (Table 4. 2). Therefore, it is inferred that the molecular orientation of the deposited pentacene respective to the surface maybe different, resulting in different hole injection efficiency, and therefore, different specific contact resistance.
(A) (B) (C)
Figure 4. 17 AFM images of 60-nm-thick pentacene deposited on HMDS-treated SiO2 substrates at various temperatures. (A) T=20℃, (B)T=50℃, (C) T=70℃.
In fact, it is similar to the 8-nm-thick samples in this case.
Bulk Resistance
From Table 4. 2, it is noted that the bulk resistance (RbS+RbD) is in fact larger than contact resistance. By the value of L0/L, it means the bulk resistance plays an important role for devices made at higher temperature especially. Moreover, the thickness of pentacene is less than the channel length, but the (RbS+RbD) is comparable to the Rch. It reveals that how to improve the bulk resistance is an issue.
Note that the deposition temperature can reduce the resistance in lateral direction of the thin-film, but have less effect in the vertical direction. The details will discuss in the 4.4-4.
4.4-3 The Resistance Extraction from PαMS-Treated Device
Figure 4. 18 Total resistance as a function of channel length at various deposition temperatures which are extracted from the electrical characteristics of PαMS-treated device.
Table 4. 3 The electrical parameters of PαMS-treated device obtained under VG=-30V.
Substrate
From Table 4. 3, it is also inferred that the channel resistance per μm depends on the deposition temperature slightly. It is probably due to the larger grain size of the pentacene and therefore, less grain boundary in the channel. However, compared to HMDS-treated device, it is less sensitive to deposition temperature (Figure 4. 16 and
Figure 4. 18).
It should be careful to use the morphology of initial layers rather than the upper layers. From the AFM images (Figure 4. 11), it shows the more blurred boundaries.
Hence, there is no obvious grain boundary to make the channel resistance to change a lot.
Minimum Effective Contact Resistance
Table 4. 3 shows that the contact resistance (RCS+RCD) reduced with contact area, corresponding to the grain boundary. From the measurement of contact angle, it is indicated that the contact area is relative to a certain surface property. To employ the deduction in the previous section, the difference of contact surface result in different specific contact resistance, i.e. hole injection efficiency. It suggests that larger contact area, which means that new area perpendicular to the substrate is produced, is
unfavorable for hole injection.
Figure 4. 19 Depiction of the two possible direction of hole injection from gold to pentacene. Yellow balls exhibit Au electrodes.
Bulk Resistance
Based on Table 4. 3, the bulk resistance (RbS+RbD) is close to the contact resistance (RCS+RCD). Note that the deposition temperature not only reduces the resistance in horizontal direction of the thin-film, but also has a little effect in the vertical direction.
In this system, the effect of Ehrlich-Schwoebel barrier is more complex: the barrier height competes against the thermal energy. At low temperature, flat-lying pentacene decreases E-S barrier, and the molecules get less energy. On the contrary, at high temperature, oblique-standing pentacene increases E-S barrier, but the molecules get more energy. Which one is more dominant should be studied.
4.4-4 Paracrystal Theory to Study the Bulk Resistance
For the films with PαMS treatment, it is uncommon to see that the intensity of XRD patterns is weaker with elevating temperature even though the bulk phase is inhibited (bottom of Figure 4. 6). In order to study how the crystalline quality in the vertical direction relates to the bulk resistance, paracrystal theory is employed.
Paracrystal Theory[24]
Crystalline quality, reflecting on the breadth of peak, is characterized by the crystallite size, and the lattice distortions of second kind. Paracrystal theory permits the separation of crystallite-size and lattice-distortion broadening provided at least two resolved reflections from a given set of planes.
2
δs= 2cosθδθ，is the total broadening excluding instrumental broadening, λ is
1.54Å for X-ray wavelength of CuKα, δθ is expressed in radians, (δs)c is the broadening from crystallite size, (δs)II is the broadening from lattice distortion of second kind, m is the diffraction order, dhkl is the spacing of (hkl) planes. Lhkl and gII are the unknowns, referred to mean dimension of cryastallites perpendicular to the plane (hkl), and mean distance fluctuation between successive (hkl) planes, respectively.
Regardless of the instrumental broadening, the squared breadths (δs)2 are plotted against m4. Lhkl and gII would be separated with intercept of y-axis, and the slope of the least-square straight line [36]as shown in Figure 4. 20.
0 50 100 150 200 250
Figure 4. 20 Plot of (δs)2 vs. the fourth power of the diffraction order.
Substrate
Distortion (%) Phase
Flat-lying
Table 4. 4 The calculation results of parameters of crystalline quality for HMDS-treated device.
Table 4. 5 The calculation results of parameters of crystalline quality for PαMS-treated device.
Lattice Distortion
For the HMDS-treated devices, it exhibits that the deposition temperature has less effect on the bulk resistance, corresponding to the little fluctuation of the second kind distortion (Table 4. 4). The lattice distortion does not improve with temperature, which is probably due to another phase occurs.
By the other point of view, we have already identified that flat-lying pentacene exists whatever the deposition temperature is (top of Figure 4. 6). By the effect of Ehrlich-Schwoebel barrier mentioned above, flat-lying pentacene might decrease the influence of temperature on E-S barrier. While the layer-by-layer mechanism works, the connected area is larger to decrease bulk resistance. This result also fits in with the assumption that the flat-lying pentacene can lower Ehrlich-Schwoebel barrier, and elevating temperature is not the only dominant factor anymore.
By the same token, the bulk resistance for PαMS-treated devices is decreased with elevating temperature, corresponding to the less fluctuation of the second kind distortion, too (Table 4. 5). It could be attributed to the inhibition of the second phase.
As to the effect of Ehrlich-Schwoebel barrier in the PαMS-treated system, it is more complex: the barrier height competes against the thermal energy. At low temperature, flat-lying pentacene decreases E-S barrier, and the molecules get less energy. On the contrary, at high temperature, oblique-standing pentacene increases E-S barrier, but the molecules get more energy. Hence, it is not as simple as the case in the HMDS-treated system.
The term gII is about 1~2%, exhibiting that the structural perfection along the normal direction is high [36].
Crystallite Size
The minimum crystallite size perpendicular to the (00l) planes is estimated to be 300~400Å, which is comparable to the film thickness (~600Å). Consequently, the effect of grain boundary is neglected, but the free-surface effect should be considered.
The grain boundary near to the free surface prefers to be perpendicular to the substrate. If the grain size is comparable to the thickness, moving grain boundary away from their groove would increase the surface energy [19]. So, it is likely the reason that post-annealing always has no concern with the morphology [37].
4.5 Turn-On Voltage
4.5-1 Turn-on Voltage Shift with Surface Treatment
-60 -40 -20 0 20
Figure 4. 21 The transfer characteristics of the OTFTs, which were fabricated at room temperature with various surface treatments, obtained under VD=-60V.
As shown in Figure 4. 21, the untreated devices present a normally on-state, while the treated ones show a normally off-state.
People have known that the dangling bonds of the oxide surface react rapidly with atmospheric water to form Si-OH groups. Once hydroxylated, the surface will cover with a 7-Å-thin layer of water even under high vacuum [38]. If the water layer is trapped at the surface while pentacene deposited, the interface traps are more relative to the pentacene/water, rather than pentacene/SiO2. Thus, the water layer is likely responsible for the trapping of the pentacene layer.
Hence, while the polar group is sheltered by the modified layer, it returns to an ideal situation which has to apply negative bias to accumulate holes. Although HMDS layer seems too skinny, it can change the OH-terminated oxide to a
(CH3)3-Si-terminated one [27], which has little polarity. This is why several molecular layers are as effective as a thicker polymer film to block the dipole field.
Figure 4. 22 Contact angles of DI water on SiO2 substrates after various surface treatments. (Left) bare substrate, (Middle) HMDS-treated substrate, and (Right) PαMS-treated substrate.
As can be seen in Figure 4. 22, it shows that the contact angle becomes small with increasing polarity. While the substrates have more strong polarity, the VT shifts toward more positive direction.
4.5-2 Sub-threshold Behavior
Schön and Batlogg have reported that the bulk trap densities of both dielectrics, Al2O3 and Kapton, are similar, but the subthreshold characteristics are widely divergent [11]. The difference is ascribed as traps at the semiconductor/insulator interface. The subthreshold swing [39] could be expressed by
)
where CS is the capacitance of the accumulation layer in the pentacene bulk. If there are a large number of interface traps, they will form a significant capacitance Cit to parallel with CS. Using above equation and substituting (CS+Cit) for CS, we obtain
where S is the subthreshold swing with interface traps, and the interface trap density Nit =Cit/e.
-2 -1 0 1 2
Gate Charge (1012cm-2)
bare
Figure 4. 23 The Subthreshold behavior of the OTFTs, applying HMDS and P MS as modified layer, respectively. It could be derived from the transfer characteristics shown in Figure 4. 21.
We have obtained a capacitance of 1.5*10-8 F/cm2 for the untreated and HMDS-treated SiO2, and 1.73*10-8 F/cm2 for the P MS -treated one. Applying Eq.(4.5B), we have received :
Table 4. 6 The calculation results of trap density from subthreshold swing.
Substrate
* Maximum trap density: density of accumulation hole + density of interface traps
Knipp et al. [4] have reported that the subthreshold swing is dominated by the material properties of the pentacene itself strongly, implying that trapping occurs in the active layer rather than in the insulators. As seen in above results, the maximum trap density of the untreated devices is much lager than that of the treated devices. It infers that the trapping form in the pentacene layer of bare substrates is different from that of treated substrates.
4.5-3 Turn-on Voltage Shift with Deposition Temperature
0.000
Figure 4. 24 The transfer characteristics of the OTFTs, which were fabricated at various deposition temperature without surface treatments, obtained under VD=-60V.
Two Gradations of Slope
From the slope of the (√-ID)-VG plots in Figure 4. 24, it can be separated into two gradations, especially at higher temperature. It is no doubt that the steeper part follows the
L WCi 2
μ term from the field-effect transistor model at the saturation
regime. But the slow part shows deviation from the ideal situation.
It is reported [40] that the humps (in the inset of Figure 4. 24) are caused by the
release of deep traps in pentacene layers which are depleted by positive biases.
However, why the heater substrates lead the VT shifts toward more positive direction, and result in a bigger current hump? (To see the following section)
Turn-on Voltage Shift
We have already known that the water layer is likely responsible for the trapping of the pentacene layer. As shown in Figure 4. 24, the VT shifts toward more positive with the devices made at higher deposition temperature. Furthermore, the slopes of first gradation extracted from the (√-ID)-VG plot exhibit that the current hump is stronger with increasing temperature. Although high temperature is adverse to water adhesion, it is possible to create a new mixture layer composed by pentacene and water through substrate heating.
Purity of the pentacene is important. For example, iodine-doped pentacene is a p-type material, but alkaline metal-doped pentacene is an n-type one [3]. If the water is doped in the pentacene through heating, the transport properties of this new layer might be different from original pentacene. A build-in potential is common to see between two types of semiconductors. Hence, it behaves like a negative bias applied by the untreated device itself.
4.6 Leakage Current
4.6-1 Channel Length Dependence of Leakage Current
-60 -40 -20 0 20
Figure 4. 25 Channel length dependence of transfer characteristics of the OTFTs which are fabricated under room temperature with (A) bare substrate, (B) HMDS-treated substrate, and (C) PαMS-treated substrate.
Poole-Frenkel Emission
For the studies of a-Si TFT, the exponential growth in current at high reverse bias is ascribed to the Poole-Frenkel emission from the defect states [9]. Moreover, for pentacene crystals, hopping is the major mechanism responsible for the carrier transport at room temperature. It is somewhat like amorphous silicon. So, if the carriers are produced by Poole-Frenkel emission, the leakage current of OTFT should
be dependent on applied electric field, and therefore, relative to the amount of carrier injection at the gate/drain overlap geometry [9].
Figure 4. 26 Band diagram of Poole-Frenkel emission.
Poole-Frenkel emission is more apparent for the untreated and HMDS-treated devices, whereas it is unclear for the PαMS-treated ones. This difference is likely due to the better crystalline quality of pentacene for the PαMS-treated substrates, leading to the barrier arising from the disorder is lower. Hence, lower barrier is insensitive to the applied electric field, resulting in unclear Poole-Frenkel emission in the PαMS-treated devices.
Channel Length Dependence
By Figure 4. 25, it is employed to investigate Poole-Frenkel region. It reveals that the leakage current not only increases obviously with higher positive bias, but also rises slightly with shorter channel length.
It is noted that shorter channel also exhibits larger gate/drain overlap vicinity, leading to more carrier injection which enhances off-current (Figure 4. 27). On the other hand, the turn-on point of the devices with shorter channels is higher than in case of longer channels. It is likely due to the carriers are depleted by reverse biases, and form a back channel.
Figure 4. 27 Illustration to show that shorter channel means larger gate/drain overlap vicinity.
4.6-2 Gate Voltage Swept in Both Directions
Figure 4. 28 The transfer characteristics of the OTFTs with (A) bare SiO2 substrate, (B) PαMS treatment, is obtained by sweeping in both directions and under VD=-60V.
There is no hysteresis [41], or memory effects, as shown in Figure 4. 28. However, it is interesting to see that the difference in off-state. The “tail” of the off-to-on curves raises with increasing positive bias (Poole-Frenkel emission), while the “tail” of the on-to-off ones preserves constant. Secondly, the curves coincide in both directions for the devices without treatments. But for the PαMS treated devices, the leakage current measured in on-to-off direction is larger one order of magnitude than the case in off-to-on scan.
While the device is operated in on-to-off scan, the interface states are filled with electrons at the beginning. If the interface traps do not function as a recombination center, electrons will be kept in the traps, and holes flow in the valence band. In this situation, off-state is dominant by the diffusion or drift of majority carriers rather than Poole-Frenkel emission. That will make the leakage current measured in on-to-off direction is larger than the case in off-to-on scan, such as PαMS treated devices (Figure 4. 28(B)).
Based on the result of section 4.5-2, the density of the maximum traps is 1.4×1013 cm-2 for the untreated device, and 4.9×1012 cm-2 for the P MS -treated one.
However, compared to the P MS -treated devices, it does not show the larger leakage current of on-to-off scan for untreated devices. It is probably due to the carrier recombination at the SiO2 surface.
CHAPTER 5
Conclusion
By varying the temperature during the deposition of pentacene, the effect of substrate temperature on the electrical performance of OTFTs, without serious disturbance of phase transition of pentacene is investigated.
Except for the serious phase transition of HMDS-treated device, and the rubber state of P MS -treated device, the mobility is promoted with less grain boundary. In order to have more insight into the real situation that how the mobility improves by varying deposition temperature in the conducting path, the transfer line method is employed.
First, the channel resistance is more sensitive to the deposition temperature due to the difference size of grain for HMDS-treated devices, while the case for P MS -treated ones is less sensitive due to no obvious grain boundary in the initial layer to make the channel resistance to change a lot. Second, the both contact resistance reduces with increasing deposition temperature, which is likely attributed from the difference of the molecular orientation. Finally, the bulk resistance should not be ignored especially for the devices with short channel. The bulk resistance is more fluctuant to the deposition temperature for P MS -treated devices, whereas the
First, the channel resistance is more sensitive to the deposition temperature due to the difference size of grain for HMDS-treated devices, while the case for P MS -treated ones is less sensitive due to no obvious grain boundary in the initial layer to make the channel resistance to change a lot. Second, the both contact resistance reduces with increasing deposition temperature, which is likely attributed from the difference of the molecular orientation. Finally, the bulk resistance should not be ignored especially for the devices with short channel. The bulk resistance is more fluctuant to the deposition temperature for P MS -treated devices, whereas the