5.3 A RCHITECTURE OF C HANNEL E QUALIZER
5.3.2 Channel equalization architecture
The hardware architecture of the proposed channel equalization is shown in Fig. 5.9. In the proposed algorithm, the hardware consists of one (2m1) bits subtractor, and (2m1+ m2) bits
registers. One register gister is for keeping
utput stable. The minuend is selected from the dividend after shifting (m2-n2-1) bits right, updates the minuend every cycle. The other re
o
Consider 2K mode here, (4K and 8K the memory storage are 2X and 4X)
Used to implement the Time domain non-causal
property
*(1-ß) H for Scatter pilot
(A<<1), and (sub<<1) (t 2. The subtrahend is the divisor. The control signals of MUX1 and MUX2 are depends on each state and sign bit of sub. The q[k] is se of th gn bit o rther e q[k] is one bit output per cycle, so it will through an S/P aft m2cycles to become ts outp ratio of working
lock rate and symbol rate is {1:m2}.
he result of subtraction) by MUX1 and MUX
inver e si f sub. Fu more, th
er an m2 bi ut. The
c
Fig. 5.9 Hardware architecture for proposed channel equalization
According to implementation loss is less than 0.15dB in equalization, we define the input and output formats are (12, 10) [28]. So we need 12 cycles for one division operation.
Furthermore, in DVB-T/H system, because of 64-Qam, it will provide a 6 times clock rate (about 54.8 Mhz) for Viterbi decoder in general design. In our design, because of other function needed, it already provides a 12 times clock rat (about 109MHe z). Here we provide two structures for comparisons. One is 12 cycle architecture, and it is the proposed design in paper. The other is 6 cycle architecture, but it still needs 12 cycles for one symbol division.
The clock rate is not fas e enough through put.
ere we can double the hardware and add some muxs to achieve the throughput.
e .10, and the 6 cycle architecture is shown in
Fig.5
t enough, so we can execute parallel to achiev H
Th 12 cycle architecture is shown in Fig. 5 .11.
Fig. 5.10 Proposed architecture for 12 cycle
Fig. 5.11 Proposed architecture for 6 cycle
The timing diagram of these two structures is shown in Fig. 5.12. We can find the output latency is one symbol in 12 cycle architecture, but the latency is two symbols in 6 cycle
We can find each operation is twice times in 6 cycle architecture. But it can be chosen by HD_A
Fig. 5.12 Timing diagram
The synthesis results and gate-level simulation results by Prime-power with UMC 0.18um cell library of divider model are shown in Table 5-3. In this table we can find in our proposed design the hardware cast can be saved 90.5%, even in 6 cycle architecture, it still can be saved 81% of the original design. Furthermore, the power consumption can be reduced 59.9%, and it still can be reduced 59% in 6 cycle architecture. And the functions are consistent in three cases.
In Table 5-4, it shows the improvements ratio in the equalizer. We can find the hardware ratio of dividers in equalizer. In original design, division gate count is 62.8% of equalizer. In proposed design, we can find the division gate count is 13.9% of equalizer. So the equalizer gate count can be reduced to 43%
power is reduced by 17% in equalizer
of original design. The hardware cost is saved by 57% and .
Table 5-3 Synthesis and gate-level simulation results Divider architecture Single cycle division
model
6 cycles 12 cycles (proposed in paper) Clock rate 9.1 (64/7) Mhz [1] 54.8 Mhz 109 Mhz
Clock period 109 ns 18.16 ns 9.08 ns
Gate count (*1) 5901 1122
(561 x 2)
564
Gate count ratio of original design
100% 19% 9.5%
Power per symbol (*2) 2.184 mW 0.686 mW (0.343 mW x 2)
0.658 mW
Power ratio of original 100% 31.4% 30.1%
design
Table 5-4 Comparisons for cost and power Equalizer Gate count
(excluding SRAM)
Power consumption
Proposed design 8103 14.92 mW
Original design[28] 18777 17.98 mW
Improvements ratio 57% (10674) 17% (3.06 mW)
Chapter 6 .
Conclusion and Future Work
After the algorithm and perform nalysis, the proposed low complexity adaptive weight channel estimator for pilot signal can improve th nce 0.3dB under dynamic channel with Doppler 60Hz. Furthermore, it will not degrade the performance, but the fixed
we in high cts.
In choosing interpolation methods, we analyze the noise term ect between polynomial interpolatio ds. In noise floor region, high order interpolation methods will get better performance. However, we should focus on the QEF region. We can find the linear interpolation will better than cubic interpolation in QEF region under channel which specified by standards.
As we kn ders cost alizer wer can be
further saved by exploiting add-shift divider structure. The modified division structure will save 90.5% hardware cost and 59.9% power consumption in divider itself. The hardware saved by 57% and power reduced by 17% in equalizer. Furthermore, this method can be used not only DVB-T/H system, but also the system which working clock rate is not the critical design issue.
ance a
e performa
ight estimator will failed Doppler effe
eff n metho
ow the divi are dominant the equ cost. The area and po
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作 者 簡 歷
姓名 ：馬英豪
學歷： 1988. 9 ~ 1994. 6 新竹縣立長安國民小學 1997. 6 新竹縣立湖口國民中學
2000. 9 ~ 2004. 6 國立交通大學 電子工程學系 學士 出生地 ：台灣省桃園縣
出生日期：1981. 12. 02
1994. 9 ~
1997. 9 ~ 2000. 6 國立新竹高中
2004. 9 ~ 2006. 7 國立交通大學 電子研究所 系統組 碩士
得 獎 事 績
2005/05 2005 全國 IC 設計競賽優等獎 2006/05 2006 全國 IC 設計競賽佳作獎
發 表 論 文
-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee, “A 1.8V 250mW COFDM Basedband Receiver for DVB-T/H Applications”, ISSCC Digest of Technical Papers, pp. 262-263, San Francisco, USA, Feb. 2006.
ing Ha Equalizer Design for
COFDM System”, 2006 IEEE International Symposium on VLSI Design, T'06), pp. 75-78, HsinChu, Taiwan, April 2006.
Yi th
2D Channel Estimation Method for DVB-T/H Application”, accepted by 17th VLSI Design/CAD Symposium, Aug. 2006.
z Lei-Fone Chen, Yuan Chen, Lu
z Y - o Ma, Lei-Fone Chen, Chen-Yi Lee, “A Channel
Automation ,and Test (VLSI-DA
z Chia-Hao Lee, Lei-Fone Chen, ng-Hao Ma, Chen-Yi Lee, “Phase Alignment wi