Based on the 2x1D linear interpolation channel estimation scheme and other low power designs such as high speed FEC decoder and dynamic scheduling FFT processor [29], a DVB-T/H baseband receiver is implemented and tapped out in Jun. 2005. The detailed structure in OFDM demodulator is shown in Fig.5.2. In the initial phase, the timing synchronizer estimates Operation Mode (2K/4K/8K), Guard Interval length, and symbol boundary with auto-correlation and power detection. Then the received signal is sent to FFT and the CFO integer is estimated with a monitor of frequency-domain signal drift. The FFT is realized with radix-8 butterfly units, a dynamic wordlength-scaling (DWC) method, and a cache-based architecture to provide 2K/4K/8K modes with less memory power. After FFT
operation, both tim a 2D linear EQ. The
sym
QAM soft-dem
of DVB-T/ es of the
original da erent channel
bandwidths will co
e that the implem
result is se
μm CMOS
table 5-1. A ing clocks with the
frequency division method. In
es 250mW power for the highest data rate 31.67Mb/s with 70Hz Doppler frequency tolerance.
e-variant CFR and CFO are estimated and tracked by
equalized signal is sent to symbol deinterleaver. Different from the general approaches, the bol interleaving is done before QAM demapping. That is because the developed 64-level apping is designed with a 24-bit input and a 36-bit output to achieve low BER H. After the de-QAM constellation, the clock rate is raised up to six tim
ta rate to satisfy the bit-level calculation. In DVB-T/H system, diff
rrespond to different clock rates. The highest clock rate of the received data is about 9MHz when the 8MHz channel bandwidth is utilized. In order to assur
ented chip can work in such condition properly, the basic clock rate of the synthesis t at 11MHz.
Power profiling and die photo of the proposal implemented in standard 0.18
process is shown in Fig.5.3 and Fig.5.4 respectively. Furthermore, chip summary is listed in 109.71MHz system clock is referenced to provide the work
tegrating OFDM demodulator and FEC designs, the proposed DVB-T/H baseband receiver consum
Fig. 5.2 Architecture of the DVB-T/H baseband receiver
Fig. 5.3 Power profiling
Channel
Fig. 5.4 Chip photo Table 5-1 Chip summary
Process 0.18um CMOS, 1P6M
Logic Gate Count
(Excluding SRAM) 371K
Embedded Memory Size 158 K bytes
Package 208-pin CQFP
Die Size 6.9 X 5.8 mm2
Input Clock Speed 109.71 MHz
Supply Voltage 1.8V Core, 3.3V I/O
Power Consumption 250mw@31.67Mb/s with 70Hz Doppler freq.
Supporting Standard DVB-T/DVB-H
Operation mode 2K, 4K, 8K
Guard Interval ratio 1/2, 2/3, 3/4, 5/6, 7/8
Modulation QPSK, 16QAM, 64QAM
5.3
In this se ted.
First, we sh hardware
cost and tak
model. Finally thod and the
implem
5.3.1
In this sec osed estimation
scheme. The performance and cost a we proposed efficiency structure. In section 2.3, the adaptive channel estim ut 0.3 dB gain below 30Hz Doppler effects. The simulation results of rough estimation for E[D2 2/X2] are listed in sect ill introduce the rough estim
hardware co transform domain processing [11] is not efficiency in DVB-T/H applications. Because, it needs take 568 points FFT and IFFT in 2K mode and only gain smaller than which mentioned in section will introduce the architecture lation with proposed adaptive channel estimator.
Fig. 5.5 s ture for 2x1D linear in 2K mode, there
are 3x1705 RAM for storing three OFDM
569 RAM for storing previous pilots. Linear interpolation ft and adder based method to implement, so the hardware cost is low. In this architecture, we can find the cost is
dominant by me combinational cost are dom plex
division operation. We will propose the modi ed architecture for complex division by low
Architecture of Channel Equalizer
ction, the detailed architecture of channel equalizer scheme will be illustra ow the proposed estimation architecture which based on the existing
e a little additional cost, which can get about 0.3 dB gain. Second, we modified the equalization architecture, and we can save a lot of hardware cost and power in division
, we will show the hardware comparisons between proposed me ented DVB-T/H receiver chip which is tapped out in Jun. 2005 [28].
Channel estimation architecture
tion, we will introduce the hardware architecture for prop re trade off, so here
ator for pilot signal will get abo
] and E[N
ion 4.3.4. Here we w ation and it only takes few
st. Furthermore, the
0.2 dB 4.3.3. Here, we
of 2x1D linear interpo
hows the architec terpolation. Consider
symbols to implement the non-causal property, and can only use shi
mory. The critical path and inant by com
fi
cost and low power issue.
ation for
i
i ples at SP
i
Fig. 5.5 The architecture for 2x1D linear interpolation channel equalization
Based on the Fig. 5.5 channel estimation architecture, Fig. 5.6 shows the estim
E[N2/X2], we estimate the noise variance by continuous pilots. We take all continuous pilots in memory, so there are 4x45 samples (45 CP subcarriers in 2K mode). We calculate each variance by four samples of CP sub-carrier, and then we average the E[N2/X2] to get the rough estimation for E[N2/X2]. The ideal value for E[N2/X2] is 10−(SNR−2.5) /10because of the boosted pilots amplitude ±4/3. The E[D2] is estimated by the previous three sam
sub-carrier, and we calculate the variance of these tree samples to be estimation for E[D2], which shows in Fig. 5.7. Based on the MSE (2-9) we can simplify it to (5-1).
2 1
{ }
In (5-1), the C1 and C2 are constants forβ∈ 0,0.25,0.5,0.75 , so we can save the coefficients into registers in advance. The coefficients are listed in table 5-2. The adaptive estimators for pilot signal architecture is shown in Fig. 5.8. In Fig. 5.8, the hardware architecture, we can find the additional hardware cost are the E[N2/X2] and E[D2] detection, one MSE comparator, several MUXs , shifter and adders, which are all combinational logic.
Furthermore, the SP distance is 12 sub-carriers, which means, we can make one βi every 12 received-data, so the hardware can be reused by efficient scheduling. In addition, the performance is mentioned in section 4.3.4.
Fig. 5.6 E[N /X ] estimation by continuous pilots 2 2
Fig. 5.7 E[D2] estimation by previous 3 samples
Table 5-2 Coefficients
β 0 0.25 0.5 0.75 table for C1 and C2
C1 0 0.0977 0.5625 1.7227
C2 1 0.6016 0.3750 0.4141
Fig. 5.8 Architecture for proposed estimation
5.3.2 Channel equalization architecture
The hardware architecture of the proposed channel equalization is shown in Fig. 5.9. In the proposed algorithm, the hardware consists of one (2m1) bits subtractor, and (2m1+ m2) bits
registers. One register gister is for keeping
utput stable. The minuend is selected from the dividend after shifting (m2-n2-1) bits right, updates the minuend every cycle. The other re
o
Consider 2K mode here, (4K and 8K the memory storage are 2X and 4X)
Used to implement the Time domain non-causal
property
*(1-ß) H for Scatter pilot
(A<<1), and (sub<<1) (t 2. The subtrahend is the divisor. The control signals of MUX1 and MUX2 are depends on each state and sign bit of sub. The q[k] is se of th gn bit o rther e q[k] is one bit output per cycle, so it will through an S/P aft m2cycles to become ts outp ratio of working
lock rate and symbol rate is {1:m2}.
he result of subtraction) by MUX1 and MUX
inver e si f sub. Fu more, th
er an m2 bi ut. The
c
Fig. 5.9 Hardware architecture for proposed channel equalization
According to implementation loss is less than 0.15dB in equalization, we define the input and output formats are (12, 10) [28]. So we need 12 cycles for one division operation.
Furthermore, in DVB-T/H system, because of 64-Qam, it will provide a 6 times clock rate (about 54.8 Mhz) for Viterbi decoder in general design. In our design, because of other function needed, it already provides a 12 times clock rat (about 109MHe z). Here we provide two structures for comparisons. One is 12 cycle architecture, and it is the proposed design in paper. The other is 6 cycle architecture, but it still needs 12 cycles for one symbol division.
The clock rate is not fas e enough through put.
ere we can double the hardware and add some muxs to achieve the throughput.
e .10, and the 6 cycle architecture is shown in
Fig.5
t enough, so we can execute parallel to achiev H
Th 12 cycle architecture is shown in Fig. 5 .11.
Fig. 5.10 Proposed architecture for 12 cycle
Fig. 5.11 Proposed architecture for 6 cycle
The timing diagram of these two structures is shown in Fig. 5.12. We can find the output latency is one symbol in 12 cycle architecture, but the latency is two symbols in 6 cycle
We can find each operation is twice times in 6 cycle architecture. But it can be chosen by HD_A
Fig. 5.12 Timing diagram
The synthesis results and gate-level simulation results by Prime-power with UMC 0.18um cell library of divider model are shown in Table 5-3. In this table we can find in our proposed design the hardware cast can be saved 90.5%, even in 6 cycle architecture, it still can be saved 81% of the original design. Furthermore, the power consumption can be reduced 59.9%, and it still can be reduced 59% in 6 cycle architecture. And the functions are consistent in three cases.
In Table 5-4, it shows the improvements ratio in the equalizer. We can find the hardware ratio of dividers in equalizer. In original design, division gate count is 62.8% of equalizer. In proposed design, we can find the division gate count is 13.9% of equalizer. So the equalizer gate count can be reduced to 43%
power is reduced by 17% in equalizer
of original design. The hardware cost is saved by 57% and .
Table 5-3 Synthesis and gate-level simulation results Divider architecture Single cycle division
model
6 cycles 12 cycles (proposed in paper) Clock rate 9.1 (64/7) Mhz [1] 54.8 Mhz 109 Mhz
Clock period 109 ns 18.16 ns 9.08 ns
Gate count (*1) 5901 1122
(561 x 2)
564
Gate count ratio of original design
100% 19% 9.5%
Power per symbol (*2) 2.184 mW 0.686 mW (0.343 mW x 2)
0.658 mW
Power ratio of original 100% 31.4% 30.1%
design
Table 5-4 Comparisons for cost and power Equalizer Gate count
(excluding SRAM)
Power consumption
Proposed design 8103 14.92 mW
Original design[28] 18777 17.98 mW
Improvements ratio 57% (10674) 17% (3.06 mW)
Chapter 6 .
Conclusion and Future Work
After the algorithm and perform nalysis, the proposed low complexity adaptive weight channel estimator for pilot signal can improve th nce 0.3dB under dynamic channel with Doppler 60Hz. Furthermore, it will not degrade the performance, but the fixed
we in high cts.
In choosing interpolation methods, we analyze the noise term ect between polynomial interpolatio ds. In noise floor region, high order interpolation methods will get better performance. However, we should focus on the QEF region. We can find the linear interpolation will better than cubic interpolation in QEF region under channel which specified by standards.
As we kn ders cost alizer wer can be
further saved by exploiting add-shift divider structure. The modified division structure will save 90.5% hardware cost and 59.9% power consumption in divider itself. The hardware saved by 57% and power reduced by 17% in equalizer. Furthermore, this method can be used not only DVB-T/H system, but also the system which working clock rate is not the critical design issue.
ance a
e performa
ight estimator will failed Doppler effe
eff n metho
ow the divi are dominant the equ cost. The area and po
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作 者 簡 歷
姓名 ：馬英豪
學歷： 1988. 9 ~ 1994. 6 新竹縣立長安國民小學 1997. 6 新竹縣立湖口國民中學
2000. 9 ~ 2004. 6 國立交通大學 電子工程學系 學士 出生地 ：台灣省桃園縣
出生日期：1981. 12. 02
1994. 9 ~
1997. 9 ~ 2000. 6 國立新竹高中
2004. 9 ~ 2006. 7 國立交通大學 電子研究所 系統組 碩士
得 獎 事 績
2005/05 2005 全國 IC 設計競賽優等獎 2006/05 2006 全國 IC 設計競賽佳作獎
發 表 論 文
-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee, “A 1.8V 250mW COFDM Basedband Receiver for DVB-T/H Applications”, ISSCC Digest of Technical Papers, pp. 262-263, San Francisco, USA, Feb. 2006.
ing Ha Equalizer Design for
COFDM System”, 2006 IEEE International Symposium on VLSI Design, T'06), pp. 75-78, HsinChu, Taiwan, April 2006.
Yi th
2D Channel Estimation Method for DVB-T/H Application”, accepted by 17th VLSI Design/CAD Symposium, Aug. 2006.
z Lei-Fone Chen, Yuan Chen, Lu
z Y - o Ma, Lei-Fone Chen, Chen-Yi Lee, “A Channel
Automation ,and Test (VLSI-DA
z Chia-Hao Lee, Lei-Fone Chen, ng-Hao Ma, Chen-Yi Lee, “Phase Alignment wi