3.1 Introduction
Metal nanocrystal charge storage offers several potential advantages over conventional stacked-gate nonvolatile memory devices
(1) A simple low cost floating-gate fabrication process.
(2) These were improved retention resulting from Coulomb blockade and quantum confinement effects that enable the use of thinner tunnel oxides and lower operating voltages.
(3) These could reduce punch-through achieved by eliminating drain-to-floating-gate coupling, allowing higher drain voltages during readout, shorter channel lengths, and smaller cell area.
(4) These were excellent immunity to stress induced leakage current and defects within the floating-gate or insulating layers due to the distributed nature of the charge storage in the discontinuous nanocrystal layer.
(5) The comfortable applications were caused by high density of states around the Fermi level and wide ranges of available work functions.
The potential for improved device performance and reliability strongly depends upon the ability to control particle core size, particle size distribution, crystallinity, area particle density, oxide-passivation quality, and crystal-to-crystal insulation that prevents lateral charge conduction in the nanocrystal layer.
As the scaling down the size of device in very large scale integrated circuits (VLSI) technology, silicides generally apply to any aspect such as lower contact resistance and fully silicide (FUSI) metal gate [3.1]. Most important of all, some reports indicate that silicide has self-passivating silicon dioxide formed under high oxidation temperature or prolonging heat treatment time [3.2]. At the same time, silicide films tended to agglomerate or form islands under such annealing condition. According to these reason, we employed this phenomenon to manufacture our metal nanocrystals embedded in the SiO2 layer. Furthermore we verified this method could have effect of memory. And this method was one step process that we can form not only the memory storage medium but also the control silicon dioxide. This process can be so simpler low cost fabrication process than traditional nanocrystal memories processes.
However, we wanted to research in the storage characteristics of the Nickel-Silicide dots so we studied on some different fabrication processes. In this letter, we proposed a NiSi2 nanocrystal memory device and studied on the memory characteristics of the metal nanocrystal.
In the Ni-Si binary system, a recent bulk annealing study [3.3] has demonstrated the existence of a NiSi + Si NiSi2 eutectoid reaction in the temperature range 690¢XC t o 735¢ XCAbove this temperature, NiSi2 rather than NiSi is stable in contact with Si. The existence of this reaction is evident in the present study as well. The reaction does not appear in the most widely accepted version of the Ni-Si + binary phase diagram [3.4]. From the eutectoid temperature up to the NiSi2 Si liquid peritectic temperature of 968GC [3.5], NiSi2 is stable in contact with Si. Below the eutectoid temperature, NiSi and Si are in equilibrium [3.6].
3.2 Experimental procedures
The experimental procedures were focus on the formation of the Nickel Silicide nano-dots. The fabrication processes of the tunneling and control oxide also went along with changes to be analyzed the nanocrsytals. Relying on the variable fabrications to obtain the three structures, we studied on the memory effect of the NiSi2 nanocrystals memories.
3.2.1 The Oxidation of the Dry Oxide/Nickel/amorphous Silicon Structure
First, the 6-in Si wafers (100) were cleaned with standard RCA recipes. The standard RCA clean process was immersed in the HCl bench at 120 for 10 minutes (called SC process). Next, the wafers were cleaned with NH4OH at 120 for 10 minutes (called SC process). The last step was dipped in HF several seconds until the backside wafer was not adhered to the DI water. Second, the wafers were followed by a thermal oxidation process to form 45A dry SiO2 layer as a tunnel oxide in an atmospheric pressure chemical vapor deposition (APCVD) furnace. Third, after the growth of tunnel oxide, Nickel thin film and amorphous Silicon film were deposited on the oxide by Dual E-Gun Evaporation System (E-Gun) at the same run. This process was deposited Ni layer then covering a-Si layer immediately. The deposition of Nickel film was the critical process to determine the result of the memory windows so checking the frequency range is necessary before deposition. The Ni was deposited about 17A with 0.1 A/sec as current range in 50-70 A and the a-Si was deposited about 150A with 0.3 A/sec as current range in 50-60 A. Finally, the furnace oxidation processes at 900 ,850 and 800 for 10 minutes in the O2 surrounding formed the NiSi2 nanocrystals and oxidized the a-Si to become SiO2 at the same time.
Moreover, the oxidation process was changed by the oxidation time. This step was prepared by the Ni silicidation furnace of the Oxidation and Diffusion Furnaces
which belonged to the Nano Facility Center of the National Chiao Tung University in the classroom (class 10k)i. We can set up the auto raising temperature to arrive at the setting temperature. When the faceplate was appeared E , we just began to calculate the oxidation time. The oxidation process was demanded for infusing into the oxygen gas so we need exchange N2 for O2 gas. The gas exchange sequences were list as
Finally, the samples were analyzed the micro-structure by Transmission Electron Microscope (TEM). Subsequently, the Capacitance-Voltage characteristics were measured at different frequency (10kHz-1MHz) by HP4284 Precision LCR Meter.
The Current-Voltage characteristics were measured by HP4156C Precision Semiconductor Parameter Analyzer. The metal insulator semiconductor (MIS) structure with NiSi2 nanocrystals embedded between tunnel and control oxide was fabricated.
3.2.2 The Oxidation of the Dry Oxide/Nickel/amorphous Silicon/PECVD Oxide Structure
First, the 6-in Si wafers (100) were cleaned with standard RCA recipes. The standard RCA clean process was immersed in the HCl bench at 120 for 10 minutes
(called SC process). Next, the wafers were cleaned with NH4OH at 120 for 10 minutes (called SC process). The last step was dipped in HF several seconds until the backside wafer was not adhered to the DI water. Second, the wafers were followed by a thermal oxidation process to form 42A dry SiO2 layer as a tunnel oxide in an atmospheric pressure chemical vapor deposition (APCVD) furnace. Third, after the growth of tunnel oxide, Nickel thin film and amorphous Silicon film were deposited on the oxide by Dual E-Gun Evaporation System (E-Gun) at the same run. This process was deposited Ni layer then covering a-Si layer immediately. The Ni was deposited about 10A with 0.1 A/sec as current range in 50-70 A and the a-Si was deposited about 20A with 0.3 A/sec as current range about 50 A. Because NiSi2
components were formed 1 2 ratio as Ni to a-Si so the thickness of a-Si layer was double of Ni layer. Forth, the TEOS oxide 200A was deposited on the Ni thin film by Plasma Enhanced Chemical Vapor Deposition (PECVD) with reactant gases of TEOS 10 sccm mixed in Nitrogen plasma at 300 . Finally, the processes were separated into two way. One of these was prepared by Metal Rapid Thermal Annealing, the N2 RTA process at 850 with several annealing time (60s, 120s, 180s, 240s and 300s).
Another was prepared by Oxidation and Diffusion Furnaces. The furnace oxidation processes at 900 and 800 for 10 minutes in the O2 surrounding formed the NiSi2
nanocrystals. This process was prepared by the Ni silicidation furnace of the Oxidation and Diffusion Furnaces which belonged to the Nano Facility Center of the National Chiao Tung University in the classroom (class 10k). Finally, the samples were analyzed the micro-structure by Transmission Electron Microscope (TEM).
Subsequently, the Capacitance-Voltage characteristics were measured at different frequency (10kHz-1MHz) by HP4284 Precision LCR Meter. The Current-Voltage characteristics were measured by HP4156C Precision Semiconductor Parameter Analyzer. The metal insulator semiconductor (MIS) structure with NiSi2 nanocrystals
embedded between tunnel and control oxide was fabricated.
3.2.3 The Oxidation of the amorphous Silicon/Nickel/amorphous Silicon Structure
First, the 6-in Si wafers (100) were cleaned with standard RCA recipes. The standard RCA clean process was immersed in the HCl bench at 120 for 10 minutes (called SC process). Next, the wafers were cleaned with NH4OH at 120 for 10 minutes (called SC process). The last step was dipped in HF several seconds until the backside wafer was not adhered to the DI water. Second, amorphous Silicon, Nickel and amorphous Silicon were sequent deposition by Dual E-Gun Evaporation System (E-Gun) at the same run. The processes were deposited 15A a-Si layer then covering 3A Ni layer and lastly deposited 125A a-Si layer. The Ni was deposited about 3A with 0.1 A/sec as current range in 50-70 A and the a-Si was deposited about 15A, 125A with 0.3 A/sec as current range in 50-60 A. Finally, the furnace oxidation processes at 900 and 800 with some different oxidation time (5, 10, 15 minutes) in the O2 surrounding were formed the NiSi2 nanocrystals and oxidized the a-Si to become SiO2 at the same time. In addition to these processes, 900 oxidation process was added with 5minutes in N2 then with 10 minutes in O2. These steps were prepared by the Ni silicidation furnace of the Oxidation and Diffusion Furnaces which belonged to the Nano Facility Center of the National Chiao Tung University in the classroom (class 10k). Finally, the samples were analyzed the micro-structure by Transmission Electron Microscope (TEM). Subsequently, the Capacitance-Voltage characteristics were measured at different frequency (10kHz-1MHz) by HP4284 Precision LCR Meter. The Current-Voltage characteristics were measured by
semiconductor (MIS) structure with NiSi2 nanocrystals embedded between tunnel and control oxide was fabricated.
3.3 Results and discussions
We wanted to overcome the problems of the Ni nanocrystals. The substitute was the NiSi2 nanocrystals memory. The Ni would prefer to react with Si more than SiO2 so the redundant Ni was not existed. However, the Ni diffusion and Ni-SiO2 interaction were solved. The NiSi2 material can be known by the materials science. The NiSi2 sintering temperature was 600-800 so our researches were focused on the temperature up to 800 . Because upper this temperature, NiSi2 was very stable component and existed less unstable component of NiSi. The one major problem of NiSi was the interface leakage current. Another problem was its less thermal stability.
But NiSi had lower resistivity than NiSi2. These were why we chose the temperature between 800-900 in our experiment. And we had some information about the NiSi2 material
(1) The barrier height to n-Si is 0.66 eV
(2) 3.63nm of resulting Nickel Silicide per nm of Nickel metal (3) 3.65nm of Si consumed per nm of metal
(4) NiSi2 would not react with Al
(5) The NiSi2 thin film resistivity was 40-50 -cm
3.3.1 Characteristics of the Dry Oxide/Nickel/amorphous Silicon Structure
The wafers were capping the Nickel thin film and a-Si film on the tunneling oxide
by the E-Gun. The experiments were researched by our group before [3.7]. So some conclusions were obtained as before. First, the NiSi2 nanocrystals were formed completely at temperature 800-900 . Second, the NiSi2 forming rate and the oxidation rate were different from 800 to 900 . The NiSi2 forming rate was faster than the oxidation rate at 900 . However, the oxidation rate was faster than the NiSi2 forming rate at 800 . This mechanism could also be proved by the a-Si/NiSi2/a-Si structure later. So our study was just repeated to make sure that the NiSi2 nanocrystals could be successful to be formed. The results were showed in the TEM images(Figure 3-4). The non-uniform nanocrystals(4~10nm) spread in the TEM images. Because the Ni film was not thin enough as we expected, the NiSi2 nanocrystals were formed too large to isolate the storage nodes. So we added one step by capping the PECVD oxide(200 A) on these structures to isolate the storage nodes. The C-V curves were measured in Figure 3-1 to Figure 3-3. The memory characteristics were appeared in these results. Nevertheless, the unobvious memory windows (~1V) were revealed the faulty condition to be formed nanocrystals.
3.3.2 Characteristics of the Dry Oxide/Nickel/amorphous Silicon/PECVD Oxide Structure
We tried to understand the characteristic of the NiSi2 nanocrystals so we did some different fabrication processes. The Ni thin film and a-Si thin film were deposited at the same time but the thickness of the a-Si film was as double as the Ni film. Therefore, the Ni/a-Si layer was prepared to form the nanocrystals only. Then, the control oxide was deposited on the NiSi2 dots by PECVD system. Finally, the Ni/a-Si was annealed in N2 with various annealing time by Metal RTA. We tried
nano-dot forming. The RTA process was specially formed the NiSi2 dots. Besides the film was RTA treated to give the atoms enough surface mobility, the film would self-assemble into a lower-total-energy state. The major driving forces contributed to this process so the film tended to break into islands along the initial perturbation. The Figure 3-6 to Figure 3-10 were showed the C-V measurement of the different annealing processes. The memory windows for different processes were approximately 1V after the forward and reverse 6V sweeping. But the memory window became small (~0.5V) after the forward and reverse 8V sweeping. The Ni diffusion into the Si substrate was unobvious in the NiSi2 nanocrystals memory because the gate injection was not occurred. Figure 3-5 was the TEM image for the 60s annealing process. We could find that the NiSi2 dots(~3nm) were formed after the RTA process. Even if annealing for the shorter time (60s), the segregation and NiSi2
formation were completed at the same time by the thermal annealing treatment.
Moreover, the nanocrystal distribution was uniform and each dot had the same distance to tunnel into Si substrate.
Next, the different fabrication processes were prepared to form the NiSi2 dot by the furnace. The samples were made the same treatment before annealing processes then NiSi2 dots were formed with different temperatures (800 , 900 ) in O2 ambience for 10 minutes. These processes could be compared with the first part of this chapter.
Figure 3-11 and Figure 3-12 were showed the C-V measurement for 900 , 800 annealing processes. The memory windows for these processes were approximately 1V after the forward and reverse 6V sweeping. But the memory window became small (<0.5V) after the forward and reverse 8V sweeping. We could find that two kind of the formation processes with metal RTA and furnace had the similar results.
This meant the NiSi2 dots were completely formed even if the fabrication processes changing. Due to the thin control oxide (~200A), the nanocrystal structure couldn t
bear the high voltage. Figure 3-13 was showed the large leakage current of NiSi2 nanocrystals memory with furnace oxidation 900 10min in O2 process. This showed that the higher voltage sweeping (8V) but less memory window. The I-V curve was also showed the inverse leakage current as the small positive voltage.
Because of the dots filled up with electrons, these were induced the inverse built-in field to dominate the leakage current as small gate voltage. But the mechanism of NiSi2 nanocrystal was not clear and definite in the unobvious memory effect. The TEM image of furnace oxidation 900 as showed in Figure 3-14 was compared with TEM image of RTA process. The thick tunneling oxide (~150A) could be observed in furnace processes so the memory windows during 8V sweeping were smaller than RTA processes. The long time for thermal treatment would enhance a-Si oxidation around the NiSi2 dots. For this reason, the a-Si consumed mostly to form the oxide and NiSi2 dots were less to be formed about 2nm-sized. Furthermore, the small size (<3nm) and sparse dot density would make the unobvious memory effect.
3.3.3 Characteristics of the amorphous Silicon/Nickel/amorphous Silicon Structure
The samples were only one step to deposit the three layers (a-Si~15A/ Ni~3A/
a-Si~125A) by E-Gun. Then, the furnace oxidation processes were completed the memory structures (tunneling oxide/ NiSi2 nanocrystlals/ control oxide). The oxidation process was the thermal treatment to be formed the NiSi2 component and segregated into low surface energy shape. Our experiments were variable with thermal treatment to make a study of forming nanocrystals. Figure 3-15 to Figure 3-18 were showed the C-V measurements for 900 annealing processes with variable
these structures could success to be formed the nanocrystals and obtained good storage characteristics. Furthermore, the variable oxidation time would improve the storage characteristic to be obtained the larger memory window. The oxidation process with N2 5minutes then O2 10minutes was derived the largest memory window (~2.7V). In addition, Figure 3-19 and Figure 3-20 were showed the C-V measurements for 800 annealing processes with variable oxidation time. The memory windows were about 2.5V after the forward and reverse 6V sweeping. The variable oxidation time would not cause the memory windows changing. The C-V curve had a strange peak between inversion region and accumulation region as the forward sweeping. But this phenomenon was not found as the reverse sweeping. The TEM image as showed in Figure 3-21 could be explained this phenomenon. One dot was closed to the substrate and the other dot was longer distance to the substrate as showed in TEM image. The difference between the forming NiSi2 rate and the oxidation rate were the reason for the two level dots at 800 . Because the oxidation rate was faster than the forming NiSi2 rate at 800 , the fringes of the NiSi2 dots would be capped with oxide immediately. The two level dots were formed as two bits of storage nodes. As the forward sweeping, the electrons filled in the dots began to erase from the nearby dots then erase from the remote dots lastly. Because of the delay time between two level dots erasion, the gate bias was not unique influence on C-V curve rising which meant from the inversion to the accumulation region. But the electrons were not filled in the dots inside as the beginning of the reverse sweeping.
So the gate voltage was dominated the configuration of the C-V curve as the reverse sweeping. Figure 3-22 was showed the large leakage current of NiSi2 nanocrystals memory with furnace oxidation 800 10min in O2 process. The I-V curve was showed the inverse leakage current as the small positive voltage. Because of the dots filled up with electrons, these were induced the inverse built-in field to dominate the
leakage current as small gate voltage. However the erasing problem as a strange peak of the C-V curve was also showed in the leakage current during the negative voltage.
These electrons in the remote dots were more difficult to erase so decreasing current as increasing voltage.
3.4 Summary
The NiSi2 nanocrystal memory will be a candidate for the metal nanocrystal memory in the future. Because of NiSi2 material is compatible with current manufacturing technology of semiconductor industry. In addition, thermal stability of the NiSi2 is another favorable quality to become nanocrystal. Moreover, the reaction between Nickel and amorphous Si had two mechanisms to be considered. Finding the optimum condition was necessary to balance the rate between oxidation and NiSi2 formation. The effective control of nanocrystal sizes could be derived from the thickness of Ni/a-Si thin films. Then, rapid thermal annealing process would be suitable for fixed nano-dots position. However, the control oxide and the tunnel oxide could be obtained completely to combine with the forming of the NiSi2 nanocrystal at the same time. The two-bits memory could be possible through adjustment of the thermal treatment with the a-Si/Ni/a-Si structure.
i Because we must change Ni silicidation furnace from medium position to below
i Because we must change Ni silicidation furnace from medium position to below