4-1-1 Motivation
When the minimum geometry in the integrated circuits (ICs) continues to shrink, the most challenging tasks in the interconnects are using new materials such as low-k and low R materials to reduce the RC delay [71]. With the reduction in capacitance, the signal propagation speed in the devices will increase and achieve a better performance. To adapt to these changes, Cu has been well accepted as the new low R material to replace Al/Cu alloy for metal interconnects in the semiconductor industry. Regarding to the low-k materials, there are various candidates such as FSG, Hydrogen Silsesquioxane (HSQ), Flare, Poly(arylene ether) (PAE), Benzocyclobutene (BCB). However, it is very hard for a low-k material to fulfill all the requirements [72]. Since HDP-USG or Sub-Atmosphere-CVD (SACVD) have been used for the dielectric layers for 0.25 µm devices, it would be easier to implement low-k CVD dielectric, such as FSG with dielectric constant lower than SiO2, for sub-0.18 µm devices. Because of these reasons, many research and development groups have investigated the feasibility of using FSG in sub-0.18 µm processes. However, there are several integration issues related to the device reliability that need to be considered before implementing FSG in sub-0.18 µm processes. Therefore, the uniformity of F distribution; F
stability under high temperature and humid environment, gap-filling capability, line-to-line capacitance reduction, and via resistance were investigated in this work.
4-1-2 Experimental Procedures
FSG films were prepared using a HDP-CVD system with gas sources of SiF4, SiH4, O2, and Ar. The USG film was also deposited in the same system with the gas source of SiH4 and O2. The substrate temperature was set at 420°C. The film thickness and refractive index of FSG films were measured using an elliposometer. The Si-F peak and F percentage were monitored by Fourier Infrared Spectroscopy (FTIR) and Secondary Ion Mass Spectroscopy (SIMS), respectively. The F% distribution was measured at the center of 8” Si wafer and at 8 mm away from the edge of the wafer. The dielectric constant was measured using a Mercury Probe at 1 MHz. On the other hand, FSG films were deposited on 2000Å USG/7000Å Al stack structure for thermal stability study. In addition, there were two kinds of cap layer for FSG used in this study: SRO and PE-OX. The SRO and PE-OX cap layer were deposited by a Plasma Enhanced CVD (PE-CVD) system. These films were annealed at 400°C for 3 h and then tested under pressure cook test at 100% RH, 120°C, 2 atmosphere for 2 h. 7000Å thick of Al patterns with metal width/gap of 0.23 µm/0.23 µm, 0.21 µm /0.21 µm, 0.19 µm /0.19 µm was used for the gap fill study. The gap fill capability of FSG films was verified by the cross-section SEM. The capacitance reduction and via resistance at different metal widths and gaps were measured by using a two-layered Al metal structure deposited with 600Å of USG liner, 8,000Å of FSG ILD layer, and 2,000Å of SRO cap layer.
4-1-3 Results and Discussions
1. F uniformity
The uniformity of F distribution in FSG films is the first integration issue we investigated. The concern for the non-uniform distribution of F is that the capacitance reduction and the device performance vary with the location of the devices on the wafer.
This will lead to a wide distribution on device performance for devices processed on the same wafer, which is not practical for manufacturing.
It has been known that the introduction of F can reduce the dielectric constant of SiO2 films [73-76]. It is because that F can reduce the ionic and electronic polarizability in the oxide films by replacing Si-O bond with Si-F or Si-O-F bonds [77]. Generally, the dielectric constant of FSG decreases with increasing the F content until it reaches the minimum and then increases with increasing the F content [76]. It has been reported that the stable FSG film happened at 3-5% of F percentage with SiF4 as the gas source [76].
As F percentage larger than approx. 4.5%, the dielectric constant of FSG film increases due to the presence of highly polar Si-O-H bond when moisture is picked up by the films.
However, the F percentage to achieve minimum dielectric constant depends on the reagents and the process conditions [73, 78].
Since SiF4, SiH4 and O2 were used as the reagent sources for film deposition, FSG films with 3.3% to 4.9% of F were deposited on Si wafers for this study. The refractive index and dielectric constant of FSG films with different F concentrations were shown in Figure 4-1-1 and 4-1-2. It shows that the R.I. decreases from 1.444 to 1.436 as the F % increases from 3.3% to 4.9%. The dielectric constant also varies from 3.35 to 3.63 depending on the F % in the FSG films. All FSG films show non-uniform F % at the center and the edge locations of 8” Si wafers. It is found that the F% in FSG films is
higher at the edge of the wafer than that at the center. The difference is about 0.2 at. % of F which represents 0.2 in dielectric constant. The higher dielectric constant of 3.6 at the center compares to dielectric constant of 3.4 at the edge. It may be caused by the plasma density non-uniformity across the wafer and the in-let of the SiF4 gas inlet location. This non-uniformity in F% and dielectric constant will cause the large variations in device performance depending on its location on the wafers
2. F stability
The second concern for the integration reliability of FSG film is the film stability.
It has been know that FSG films are not stable if the F % is too high and reduces its resistance to moisture [73]. The absorbed moisture in FSG films will react with the Si-F bonds and become Si-O-H and HF. The increasing in highly polarized O-H bond will increase the dielectric constant. In addition, the HF and F diffused out of the films at high temperature will react with Al lines resulting in the Al corrosion [79].
The F stability in FSG film without any cap layer was under PCT for 2 h and 400°C annealing for 3 h was shown in Figure 4-1-3. The data shows that the F in FSG decreases from 3 x 1021 atoms/cm3 at the FSG/USG interface to 2 x 1021 atoms/cm3 at FSG/air interface. It indicates that F is not stable in FSG films and diffuses out of the films after the PCT and 400°C annealing.
It has been suggested that FSG films can be capped with 200 to 500 Å oxide film to prevent F diffusion out of the FSG film and enhanced the stability of FSG film [80]. In addition, exposing FSG to the CMP slurry will form HF due to the F dissolving in water.
This cap layer can prevent FSG from direct contact with CMP solution. Therefore, two different cap oxide layers, SRO and PE-Oxide, as the diffusion barriers for HDP-FSG
were studies.
FSG films capped with SRO before and after PCT and 400°C annealing were shown in Figure 4-1-4 and 4-1-5, respectively. The FSG film capped with SRO shows that the F concentration is slightly lower than that before tests. It indicates that there are some F atoms depleted in FSG films. However, the F concentration is still very low before and after PCT and 400°C annealing at SRO/air interface. Instead, F concentration is slightly higher at the SRO/FSG interface after tests. This indicates that SRO layer can be a good barrier layer for F diffusion. In Figure 4-1-6, FSG film with SRO cap layer still remained stable after 48 h in ambient, PCT and annealing test. The depleted F in FSG film was accumulated at the SRO/FSG interface. For FSG films capped with PEOX, the F diffused into PEOX cap layer and generated an F concentration gradient in PEOX layer and FSG layer close the PEOX/FSG interface as shown in Figure 4-1-7. This indicates that using PEOX as the FSG cap layer can not block the F diffusion.
3. Gap-Filling Capability
The third concern for the integration reliability of FSG is the gap fill capability.
As the minimum geometry of IC devices becomes smaller and smaller, the gaps between metal lines become smaller as well. Since the film deposition rate is lower at the side wall of metal gaps than at the bottom of the gap, there is a limitation for the smallest gap that dielectric film can fill it by CVD method. If the deposition rate is too fast, it will generate the voids in the gap. It has been reported that HDP-CVD can enhance the gap fill capability of USG for 0.25 µm processes due to the slower deposition rate of HDP [73].
In addition, F in SiO2 may facilitate the deposition to fill a smaller gap. In the 0.18 µm design rule, the minimum metal gap should be close to 0.23 µm. Therefore, HDP-FSG
film needs be able to fill metal gap smaller than 0.23 µm before it can be used for 0.18 µm processes.
The gap fill capability was investigated by depositing FSG films on pattern wafers with different metal width/gap: 0.23 µm/0.23 µm, 0.21 µm/0.21 µm, and 0.19 µm/0.19 µm. The results show that FSG films can fill all 0.23 µm/0.23 µm patterns at the center and the edge pattern in the wafers as shown in Figure 4-1-8 and 4-1-9. However, FSG films can fill the 0.21 µm/0.21 µm patterns at the center but not the 0.21 µm/0.21 µm at the edge of wafer. Especially, the gap fill is the worst for gaps in the wafer at notch area (Figure 4-1-10). For 0.19 µm/0.19 µm patterns, large holes were observed both in the center and the edge of wafer. It is found that the aspect ratio is approx. 3.4 at the center of wafer, is approx. 3.8 at the edge of wafer, and is approx. 4 for wafer notch region.
Apparently, the FSG can only fill the 0.21 µm/0.21 µm gas with aspect ratio up to approx.
3.6 and there is void generated when the aspect ratio increases to 3.8. Therefore, with the capability of filling 0.23 µm/0.23 µm gaps, FSG can still be used for 0.18 µm processes.
4. The capacitance reduction and via resistance
The last concern for the reliability is the capacitance reduction and via resistance of FSG film. Since the purpose of using low-k materials is to reduce the capacitance for smaller geometry, the capacitance reduction will direct affect the device performance. In addition, the via resistance for FSG film needs to be investigated to ensure that FSG can be processed without affecting the via yield. Since SRO is good diffusion barrier for F, devices with 600Å USG/8000Å FSG/2,000Å SRO sandwich structures were processed for capacitance and via resistance measurement.
The line-to-line capacitance of patterns with FSG as the dielectric layer was
measured at different metal widths and gaps. For the metal line-to-line capacitance, it was found that the there was approx. 7.45% to 7.7% reduction in capacitance for 0.23 µm/0.23 µm pattern and approx. 6.75% to 7% reduction in capacitance in 0.23 µm/0.46 µm pattern as shown in Figure 4-1-11 and 4-1-12. In addition, the capacitance reduction also varies with the metal width as shown in Figure 4-1-13. It shows that FSG with wider metal line has a larger impact than the thinner metal line on the line-to-line capacitance. It is believed that the larger capacitance observed at wider metal lines is due to a larger fringe capacitance between wider metal lines. The via resistance of FSG at different unlanded via mis-alignment is shown in Figure 4-1-14. It shows that the FSG has similar unlanded via resistance to USG. It is consistent with the results that FSG can have similar via yield as USG.
4-1-4 Summary
In our study, it was found that there is approx. 0.2 % of F variation between the center and the edge of wafers. This non-uniform F distribution leads to the variation in dielectric constant for about 0.2 at the center and the edge of wafers. Because of that, the device performance will vary for devices processed on the same wafer and it will be a concern to put FSG into production. The SIMS data shows that the thermal stability of FSG can be enhanced by using a cap layer and SRO is superior than PE-OX in blocking the F diffusion at high temperature and moisture environment. HDP-FSG can fill the gap as small as 0.23 µm gap which indicates that FSG can be used for the 0.18 µm processes.
However, it will be more difficult to use FSG in process less than 0.18 µm. In 600Å USG/8000Å FSG/2,000Å SRO cap layered structure, HDP-FSG shows 7.45 to 7.7%
line-to-line capacitance reduction and has similar via resistance to that of USG film.
Therefore, HDP-FSG with SRO cap layer can be used for 0.18 µm processes if the issue of the F% variation in the FSG film can be improved.