4-5-2 Integration of a Stack of Two Fluorine Doped Silicon Oxide Film with ULSI Interconnect Metallization
III. Integration Features
A partial integrated structure with the vias hole is reported in Figure 4-5-7. The via hole’s critical dimension (CD), dry etch rate and chemical mechanical polishing rate has been listed in Table 4-5-2. The CD showed no significant differences for the two (2) different schemes. The via etch had been performed using the Applied Materials HDP etcher system. The etching rate was measured at 143.2 nm / min. HDP-CVD FSG film,
and 158.3 nm / min. for the PE-CVD FSG layers. In comparison, the undoped PEOX and PETEOS film etch rate was measured at 140.5 nm /min. This is lower than the FSG layer’s. In a FSG film’s stack, the mechanical polishing process was performed on PE-CVD FSG film. The PE-CVD FSG film’s polishing rate (289.6 nm /min) was 40 nm and 60 nm higher than those of the HDP-CVD FSG layer and undoped PE-CVD oxide film on a blanket wafer. The same trend was found on pattern wafers. That is, it is as beneficial for improving throughput as taking two (2) stack FSG films as the IMD scheme. Considering the global planarization’s effect, the HDP-CVD FSG layer’s profile on control wafer would collapse at 85 mm from the wafer edge. This is because the smaller chamber spacing for the HDP-CVD hardware design was limited. However, no such phenomenon was found with PE-CVD FSG film, as shown in Figure 4-5-8. The 5th interlayer FSG film’s edge profile was in a pattern wafer after CMP process, the collapse location on wafer’s edge was extended from 85 mm to 95 mm (shown in Figure 4-5-9), which provides an improvement in total wafer edge yield.
IV. The capacitance reduction and via resistance
Because the purpose of using low-k materials is to reduce the capacitance for smaller geometry, the capacitance reduction will directly influence the device’s performance. The line to line capacitance of patterns with different FSG IMD structures was measured at different metal widths and gaps. The line to line capacitance reduction for the stack FSG films varies with the metal spacing is shown in Figure 4-5-10. It indicates that wider metal spacing has a smaller impact than the thinner metal spacing on the line-to-line capacitance. The larger capacitance observed at wider metal spacing is the result of a larger fringe capacitance between the wider metal spacing. Comparing with
different inter-metal schemes with different metal spacing / widths, it shows that Si-rich oxide with 30 nm thickness was induced to decrease average line to line capacitance reduction from 12% to 10-11%. In addition, in comparing the full HDP-CVD FSG layer and stack layers, the line to line capacitance reduction was found comparable, which achieves a 10-11% reduction when compared to undoped silicon oxide film. A stack of FSG film’s via resistance needs to be investigated to ensure that a stack of FSG scheme can be processed without affecting the via yield. The different IMD layer’s via resistance at a different via hole is also checked. If compared with the full HDP-CVD FSG case, Rc_via for IMD consisted of a stack of HDP-CVD and PE-CVD FSG that was comparable with a full HDP-FSG scheme. Nonetheless, the Rc-via’s variation is considered insignificant. The conclusion shows that a stack of HDP-CVD FSG and PE-CVD FSG film as IMD is suitable and reliable for low-k applications on the sub-micron processes.
4-5-4 Summary
The stack made of 0.6 µm thick HDP-CVD FSG film for gap-filling and followed by capping with 1.1 µm PE-CVD FSG films is a good compromise to fill narrow gaps between metal lines, to reduce the capacitance in the plane and between metal levels, and to optimize the throughput on a global isolation structure. Additionally, to prevent poor adhesion due to fluorine diffuse into metal layer, 30 nm thick SRO film was deposited prior to HDP-CVD FSG film. It has successfully demonstrated promising film properties as well as easy drop-in device and process integration feasibility for IMD applications in sub-0.18µm generations. No significant issue has been shown to realize the partial
integration of FSG films. On the other hand, implementing a stack of FSG layers as the IMD for the interconnect of the 0.18 µm generation exhibited 10-11% gain in the ring-oscillator’s RC delay. Based on the electrical and reliability test results, it is believed that this stack deposited of HDP-CVD FSG film capped with a PE-CVD FSG layer is a good candidate for advanced sub-micro intermetal dielectric.
Figure 4-1-1. The R.I. of FSG films with different F concentrations at the center and the edge of wafers.
1 .4 3 6 1 .4 3 7 1 .4 3 8 1 .4 3 9 1 .4 4 1 .4 4 1 1 .4 4 2 1 .4 4 3
3 3 .5 4 4 .5 5
F C o n c . ( % )
Refractive Index
C e n t e r E d g e
Figure 4-1-2. The DK of FSG films with different F concentrations at the center and the edge of wafers.
3.3 3.35 3.4 3.45 3.5 3.55 3.6 3.65
3 3.5 4 4.5 5
F co nc.(% )
Deilectric Constant
Ce n t e r Ed g e
Figure 4-1-3. The F concentration of FSG film without cap layer after PCT for 2 hrs. and annealing at 400°C for 3 hrs.
0.0E+00 5.0E+20 1.0E+21 1.5E+21 2.0E+21 2.5E+21 3.0E+21 3.5E+21 4.0E+21
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Depth ( micron)
F conc.(atoms/c.c.)
FSG USG Al
Figure 4-1-4. The F concentration of FSG film with SRO cap layer as deposited.
0.0E+00 1.0E+21 2.0E+21 3.0E+21 4.0E+21
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Depth (micron)
F conc.(atoms/c.c.)
SRO FSG USG Al
Figure 4-1-5. The F concentration of FSG film with SRO cap layer after annealing at 400°C for 3 hrs.
0.0E+00 5.0E+20 1.0E+21 1.5E+21 2.0E+21 2.5E+21 3.0E+21 3.5E+21 4.0E+21
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Depth (micron)
F conc.(atoms/c.c.)
SRO FSG USG Al
Figure 4-1-6. The F concentration of FSG film with SRO cap layer after PCT for 2 hrs.
and annealing at 400°C for 3 hrs.
0.0E+00 5.0E+20 1.0E+21 1.5E+21 2.0E+21 2.5E+21 3.0E+21 3.5E+21 4.0E+21
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Depth (micron)
F conc. (atoms/c.c. )
SRO FSG USG AlFigure 4-1-7. The F concentration of FSG film with PEOX cap layer after PCT for 2 hrs.
and annealing at 400°C for 3 hrs.
0.0E+00 5.0E+20 1.0E+21 1.5E+21 2.0E+21 2.5E+21 3.0E+21 3.5E+21 4.0E+21
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Depth (micron)
F conc.(atoms/c.c.)
PEOX FSG USG Al
Figure 4-1-8 Different Patterns at Center of the wafer
Figure 4-1-9 Different Patterns at Edge of the wafer
Figure 4-1-10 Different Patterns at Notch of the wafer
97
Figure 4-1-11. Line-to-line capacitance of FSG and USG for a 0.23/0.23 metal structure.
Cumulative Probability
0.1 1 10 30 50 70 90 99 99.9
Capacitance (F)
1.3e-11 1.4e-11 1.5e-11 1.6e-11 1.7e-11
FSG USG
98
Figure 4-1-12. Line-to-line capacitance of FSG and USG for 0.23/0.46 metal structure.
Cumulative Probability
0.1 1 10 30 50 70 90 99 99.9
Capacitance (F)
8.0e-12 9.0e-12 1.0e-11 1.1e-11 1.2e-11
FSG USG
99
Figure 4-1-13. Normalized line-to-line capacitance of FSG and USG for different metal structure with 0.23 µm gap.
0.4 0.5 0.6 0.7 0.8 0.9 1
0 0.2 0.4 0.6 0.8
Metal Width (micron)
Capacitance (Normalized)
FSG USG
100
Figure 4-1-14. Normalized via resistance of FSG and USG for different mis-alignment of 0.26 µm via.
0.98 1 1.02 1.04 1.06 1.08 1.1 1.12 1.14
0 0.02 0.04 0.06 0.08 0.1
Mis-alignment for unlanded via (micron)
Via Resistance (normalized)
FSG USG
101
Table 4-2-1. The property of FSG film trends at 350o-450oC deposition temperature
Deposition RateFluorine Concentration
% at. F
Dielectric Constant k
Refractive index
RI Stress Wet Etch rate WER
Hardness H Deposition Temperature
102
Table 4-2-2. The effect of deposition temperature on gap-filling parameters of FSG process.
Deposition Temperature
(oC)
Deposition rate D (Å/min)
Sputter Rate S (Å/min)
Etch Rate
E (Å/min) E/(S+E) E/S D/(S+E) D/S D/E E/S
350 3607 1541 1011 0.396 0.656 1.374 2.341 3.568 0.656
375 3553 1548 1028 0.399 0.656 1.340 2.295 3.456 0.664
400 3506 1553 1067 0.407 0.687 1.300 2.258 3.286 0.687
425 3480 1538 1080 0.412 0.702 1.291 2.263 3.223 0.702
450 3393 1542 1112 0.419 0.721 1.241 2.200 3.052 0.721
103
Table 4-2-3. TDS analysis for FSG films with varying deposition temperatures.
Deposition Temperature
(oC) 350 400 425 450
Ar onset of evolution (oC) 450 455 445 467
Ar peak pressure (10-7 Torr) 0.1 0.1 0.1 0.1
H2O onset of evolution (oC) 452 467 467 520
H2O peak pressure (10-7Torr) 1.0 1.0 1.0 0.5
F onset of evolution (oC) 435 450 467 490
F peak pressure (10-7 Torr) 1.0 1.0 1.0 0.5
HF onset of evolution (oC) 410 420 450 467
HF peak pressure (10-7 Torr) 1.0 1.0 1.0 0.5
104
Figure 4-2-1. The effect of deposition temperature on the concentration of fluorine and refractive index for FSG film.
3 3.5 4 4.5 5
350 375 400 425 450
Deposition temperature(oC)
% at. F (Si-F/ Si-O peak ratio)
1.42 1.43 1.44 1.45 1.46
Refractive Index (633nm)
% at. F (FT-IR) Refractive index
105
(a)
(b)
Figure 4-2-2. The concept of HDP-CVD gap-filling: (a) HDP-CVD, (b) F doped HDP-CVD.