A Low Power Multi-band Selector DLL with Wide-Range Locking
B. Charge Pump circuit (CP)
Figure . 3 Charge Pump circuit
In the design of charge pump, the ones that should pay attention to are the mismatch phenomenon of the current. When reference pulse and feedback pulse are the same phase place, UP and DN signals produce a very short pulse to reduce deadzone at the same time. This situation can cause charging and discharging the switch and shorting out at the same time in the charge pump. If the current charged and discharged at this moment are not equal, it will make the voltage of control in the delay cell locked and produce skew. The unstability may lead the circuit unable to lock. Therefore, it needs to minimize the mismatch of the current in the design. Fig. 3 shows that UP and DN switch connect with one PMOS and NMOS. It is used for dispelling the switch charge sharing effect to filter capacity. In order to consider channel length modulation effect, transistor length of charge pump needs to be slightly greater than the minimum length.
C. voltage-controlled oscillator (VCO)
Two kinds of oscillator models are used in CMOS technology. One is L-C tank and the other is ring oscillator. The ring oscillator can reaches the demand narrated above. Therefore ring oscillator is adopted. The advantage of ring oscillator lies in that the circuit only needs small area, low power consumption, and wide frequency range. Especially that the delay cell is single-end, and compare to the delay cell with differential configuration, the necessary area of chip and power of consuming are smaller. This circuit adopts ring oscillator made up by current-starved invert[6]. It charges and discharges controlled by M3 and M5. M3 can be regarded as a source of current( Iref) controlled by Vcon, and determines the upper limit of the current that invert charges
and discharges. Vcon with comparative low-voltage will reduce the discharge current. It will make invert output to be increased by the transition from high to low. Similarly, charging the current to control by M5 of invert, it can also be regarded as M5 as the current source ( Iref) Fig.4 (b). The ring oscillator is configured by five stages of delay cell. It exhibits wide operating frequencies.
Fig.4 （a）Current-starved flip-flop (b) ring oscillator composed of Current-starved inverts
D .
Introduction to Pulse-swallow counter principle:Pulse-swallow counter is constituted by dual-modulus being divided by N/N+1 prescaler and program, and swallow counter. The circuit is shown in Figure. 5 (p and S counter stand for Program, and swallow counter). The principle of Pulse-swallow counter described as follow: first, dual-modulus Prescaler is divided by N+1. After divided by N+1, the signal of VCO is sent to P
and S counter, which should be greater than S counter. Thus S counter will go back to zero faster than P counter. Until P counter stops counting, the above movement ends before pulse-swallow counter returns to zero and starts counting again. A pulse-swallow counter totally counts (N +1) × S + N × (P − S) = NP + S times. Therefore, proper choice and change of the value of N, P and S
Plus swallow frequency divider block diagram
in out
Figure. 5 Pulse-swallow counter
Prescaler is another high frequency unit in the frequency synthesizer during the operating process. It requires high speed. This circuit is the application of dual-modulus prescaler（16/17）
on high frequency synthesizer. Prescaler is constructed by a simultaneous dividing 4 and 5 circuit, non-simultaneous dividing 4 circuit, and other logic gate. Owing to the dividing 16/17 circuit should be operated in high frequency, its flip-flop should use DFF. It also implemented by the circuit of TSPC[7].
Figure. 6 Prescaler 16/17 diagram
÷
4/5 circuit is shown in the solid line in Figure 6. The operation sequence is similar to Figure 4:when MC=0, DFF3 has no reaction. When MC=1, DFF1 to DFF3 forms
÷
5 circuit. When 16/17 circuit is in mode=0, MC=0 goes through 4/5 circuit to divide 4 and then non-simultaneously using÷
4 to divide 4. The end is a÷
16 circuit. When mode=1, the circuit is a dividing 17 one because of except 4 circuit first three cycles, 4/5 circuit is one to be divided by 4 circuit, is activated only in last the cycle when MC=1 for÷
5 circuits. Therefore it is divided by 4 × 3＋5 × (4－3) = 17.Figure 7 Timing diagram of the
÷
4/5 dividerThe prescaler used here is the same as the one shown in Figure. 6. The programmable down counter is the the same with the swallow counter. The counter is mainly composed of counter cells, which is shown in Fiqure. 8 (a). The TFF in the counter cell is obtained by connecting D and Q of the DFF in Figure. 8 (b).
(a)
(b)
Figure 8 Schematic of (a) programmable counter, and (b) the counter unit in (a)
When LD = 1, the counter is programmed by presetting or resetting the flip-flops according to program input. When LD becomes 0, the counter starts to count down. If the output fout is connected back to LD, an output pulse of fout reload the program input and the counter starts counting down from the preset program value. Another output pulse appears when the counter counts down to zero and a new cycle begins. Therefore, the down counter in this configuration can be used as a frequency divider. We take the divide-ratio N=(n3 n2 n1 n0)2=(1 0 0 0)2 =8 as an example. Figure 9 is the associated timing diagram. As long as the state of the number Q=(q3 q2 q1 q0) is not equal to zero, the counter outputs a signal 0. The counter keeps counting down until Q becomes zero. In this instant, fout (LD) becomes 1, and hence a new cycle begins.
Figure 9 Timing diagram of the 4-bit programmable down counter.