Chip Implementation

Concerning the chip implementation, the cell-based design flow with Artisan standard cell library is adopted and the proposed architecture has been implemented in TSMC 0.18-um CMOS process. The Synopsys Design Compiler is used to synthesize the RTL design of the proposed architecture, the Cadence SOC Encounter is adopted for

placement and routing (P&R) and the Synopsys PrimePower is used to measure the power consumption for each mode after post-layout simulation. Table 4.3 summarizes the chip characteristics of the proposed architecture.

Table 4.3. Chip characteristics of the proposed architecture.

Active Chip Area 1.13 x 1.13 mm²

Gate Count 97, 246

Max Clock Frequency 100 MHz

Process Technology TSMC 0.18-um CMOS

Power Consumption (mW) @ 100MHz

One-Plane Type 22.75 Two-Plane Type

(rising/vertical/horizontal)

51.76/56.25/71.9

Two-Plane Type (falling) 57.63 Uncompression Mode 38.63 Power Consumption

(mW) @ 66.7MHz

One-Plane Type 15.18 Two-Plane Type

(rising/vertical/horizontal)

34.52/37.51/57.26

Two-Plane Type (falling) 38.43 Uncompression Mode 25.76

Fig. 4.6. Chip layout of the proposed architecture.

Chapter 5

Conclusion and Future Work

In this work, the reconfigurable algorithm for depth buffer compression is presented. This proposed algorithm not only supports the 1-bit HA, 2-bit DDPCM schemes as well as 7-bit DDPCM scheme, but also handles one-plane and one-plane type compressions. In addition, different compression schemes can be applied in the vertical and horizontal parts in a tile. There are totally 11 compression modes adaptively applied according to different 3D scenes in this proposed compression algorithm. In two-plane type, there are four kinds of combination cases, including rising, vertical, horizontal, and falling cases, concerned in the presented algorithm.

For 8x8 tile size with 16-bit depth values under the teapot benchmark, the proposed reconfigurable algorithm can achieve CR of 1.75 on average and improve 13.6% and 31.6% compared with the HA and DDPCM compression methods, respectively. For 8x8 tile size with 16-bit depth values under the Stereoscopic polygons benchmark, the proposed reconfigurable algorithm can achieve CR of 1.74 on average and improve 21.7% and 38.1% compared with the HA and DDPCM compression methods, respectively.

Furthermore, the proposed reconfigurable and power efficient depth buffer compression architecture has been verified and implemented in TSMC 0.18-um CMOS process. The core consists of 97,246 transistors, and its area is 1.13 um². It operates at 100 MHz with maximum power consumption of 38.63 mW in uncompression mode,

22.75 mW in one-plane type, 51.76/56.25/71.9 mW in two-plane type, including rising, vertical, and horizontal cases, and 57.63 mW in two-plane type, including falling cases, at supply voltage of 1.8V.

For the future work, the ranges of horizontal and vertical parts will be discussed for better compression performance.

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