Circuit technique in SRAM peripheral circuit

Fig. 2.22: Lowering the WL voltage improves read noise margin, and the Gate controller improves PVT variation impact. [2.26]

In [2.26], this design is in 45-nm technology and it use some assist circuit to improve read and write ability of conventional 6T cell, Fig. 2.22. Its key point is to decrease the voltage of word-line to improve the read margin. Another issue is to increase immunity against temperature. Fig. 2.22 shows the assist circuit. The design uses resistance instead of PMOS to compose the circuit because the temperature has larger influence on PMOS than on resistance. There are R1 and R2 in gray block. The key point is to use different voltage NB by R1 and R2, and the feedback loop to adjust the WL voltage.

Fig. 2.23: By floating bit-cell supply voltage, write margin can increase. [2.26]

A good way to improve WM is to decrease the supply voltage of cell. The authors in [2.26] use floating technique to achieve this objective. They use 8 cells as a group because it is the optimization results by testing, Fig. 2.23. These assist circuits help the 6T cell work perfectly under 45-nm technology, but the drawback is to increase the complexity of peripheral circuit. However, the 6T cell has the smallest area compared to other cell structure and the lowest power consumption.

Fig. 2.24: Another layout style - Reaction diffusion bit-cell. [2.28]

RD cell [2.27-28] (Rectangular Diffusion Cell, Fig. 2.23) may be a method to solve variation in future process. It means that the beta ratio equals 1. Although beta ratio should be large enough to keep the read margin, sometimes there are some different lengths or widths occur in this layout of cell due to the process variation. For example, the two sides of passgate don’t have the same width while there is a process offset. In future process, this issue becomes more serious and worse. Because the length and width is smaller than before, the contact area can’t scale down with that. It needs to change the contact layout style in order to prevent PMOS and passgate’s diffusion damage from contact due to process variation.

The RD cell has another advantage: the electric beta ratio in RD cell is better than that of conventional cell. Driver ability of passgate transistor to pull-down transistor is defined as electric beta ratio. In low voltage operation, due to reverse narrow channel effect, the electric beta ratio decreases. It means the conventional cell have some problem in read stability. But RD cell will not happen. Also, using this style, the area is smaller than conventional cell because of its large beta ratio.

Fig.2.25: Several techniques to reduce power in stand-by mode [2.29]

In Fig. 2.25 [2.29], authors use “sleep transistor” to reduce the power. If the cell bank has no write or read, the cell bank will be operated in sleep mode. Lowering the supply voltage, power gating, eliminating the bit-line precharge, and adjusting body bias reduce the leakage consumption.

Fig. 2.26: Hierarchical architecture can lower power consumption by reducing the local bit-line capacitance. [2.30]

In [2.30], it uses hierarchical architecture to design the SRAM. If the SRAM’s

capacity is large, we often use one bit-line to connect 1024 or 512 bit cells. As a result, the capacitance on bit-line is very huge. Only one cell can do read or write operation in one bit-line. It is necessary to pull down or pull up the voltage of bit-line in every read or write cycle. If the bit-line design uses hierarchical structure, which only connects 16 cells, can reduce the power significantly, Fig. 2.26. In addition to hierarchical, it also uses word-line pulse to reduce the voltage difference. This design can lower the power effectively, but it needs to use many local amplifier and buffer to keep the correct the signal.

Fig. 2.27: An improved replica circuit generating the exact timing for word-line can reduce SRAM power [2.31]

In [2.31], this paper talks the conventional replica circuit and the circuits can work fail against variation. Because of variation, some read/write operation in cell is faster or slower than normal cell. An error may happen while there are fast replica cells and slow array cells in one SRAM. It use asymmetrical cell to make sure the sufficient operation time for array cell, Fig. 2.27.

Fig. 2.28: By using several replica cells in one replica column can against serious PVT variation which happens in replica column. [2.32-33]

In [2.32-33], the authors use many replica cells to do the operation together and found that it is more stable to against temperature and process variation. Because sometimes the array has good yield and there is a serious variation in one of replica cells, the SRAM still can work correctly.

Fig. 2.29: MTCMOS technique: improve performance and reduce power in low voltage operating. [2.34]

In [2.34], MTCMOS technique is applied to low-power and high speed SRAM. Use

low Vt logic in critical path to speed up and high Vt logic in other block to reduce leakage power [2.34]. Besides, it also use multi-voltage to design the SRAM, some blocks need high speed by using high voltage and some blocks use low voltage to reduce power consumption, as shown in Fig. 2.29.

2.5 Summary

This chapter introduces traditional 6T SRAM structure, operation and other new SRAM design for low power in recent years. Due to the properties of advanced process technology, traditional 6T SRAM contrarily become a bottleneck in chip performance. As a result, lots of probable substitutes for traditional 6T SRAM or novel assist circuits are presented in recent years. Besides, ultra low power application such as mobile device, wireless sensor and medical device might require embedded memory working successfully with ultra low/low supply voltage. Obviously, 6T SRAM can’t satisfy the demands. Following chapters will present the influence caused by advanced process on SRAM, a replacement of traditional 6T bit-cell and a multi-port SRAM based register file with wide operating voltage range.