Design implement

5.5 Design implement

Fig. 5.21 shows the floorplan and layout of proposed register file. Considering to

shuttle of UMC 90nm process in 2009, it is necessary to decrease area to ensure this design can tapeout. Therefore, the capacity of proposed register file in layout is 4KB.

In other words, the data-length is decreased from 32-bit to 8-bit, and the other design and feature is remained, such as bit-interleaving - 4, 4 banks, 4W/4R …etc. The area composition is following: input/output circuit in 9%, switch circuit in 24%, decoder and driver in 27%, array in 15%, and MOS capacitance in 2.9%...etc.

Fig. 5.21: Layout photograph of the proposed sub-threshold multi-port register File.

5.6 Simulation results

The proposed 4W/4R 16KB low power multi-port register file with wide operating voltage range is implemented in UMC 90um CMOS technology. It can operate at 433MHz at 1V, 48MHz at 0.5V and 485 KHz at 0.25V, respectively. While the register file works under 433MHz for 4 simultaneous accesses, it consumes 4.97mW and 2.53mW during write and read operations respectively. When it works under 485 KHz for 4 simultaneous accesses, it consumes 22.3uW and 22.9uW during write and read operations respectively. In most of the time, operating voltage of low power application is under 0.5V or below. High voltage operating for performance is only in a short period of time. This proposed register file can achieved the requirement.

Besides, here is the composition of power consumption: 48% in array, 26% in decoder and driver, 16% in switch circuit and 10% in other circuits.

Table 5.1 shows the layout micrograph of proposed register file. Furthermore, by increasing more area of MOS capacitance of boosting and negative voltage generator in original design, operating voltage of this proposed register file can scale down to 0.18V. In 0.18V, proposed register file work successfully across varies process and temperature variation. Even though increasing more area on MOS capacitance, it works still fail at 0.17V or below due to the large gate leakage and sub-threshold leakage in worst corner. Fig. 5.22 shows access time in FF 75°C corner is 254X times in SS -15°C corner while operating in deep sub-threshold region.

Table 5.1: The simulation results.

Configuration 4W/4R 4x128x32bits

Technology UMC 90nm CMOS

Operating Voltage 1V 0.5V 0.25V

Max. Frequency 433MHz 48MHz 485KHz Max. Read Power 2.53mW 443uW 22.3uW Max. Write Power 4.97mW 823uW 22.9uW

Fig. 5.22: Access time significantly varies across process and temperature variation.

Fig. 5.23: The power comparison between this work and conventional design.

In Fig. 5.23, power comparison between this work and conventional design is shown. Conventional 8T bit-cell design without the proposed read scheme works fail due to large leakage current below 0.5V. By using the proposed scheme such as the controllable precharge scheme and improved read stack, the read power consumption is reduced to 75%. The reason of write power increase is that the large capacitance of

negative voltage generator. However, theses proposed scheme make the register file still operates successfully in 0.25V or below, and it is the main target. In 0.25V, the power consumption is less than 0.05% of conventional design in 0.5V. Since this proposed register file is for low power / low voltage application instead of high performance, it can be applied to sub-threshold application.

5.7 Summary

A low power multibank architecture for simultaneous access with collision detecting technique is presented. For the case the performance is non-critical, the supply voltage can operate at sub-threshold region (<0.5V). A new dual Vt 8T bit-cell, negative voltage write scheme with local BL sensing logic, and read scheme with read footer improvement, controllable pre-charge scheme and read replica circuit are proposed. A 4W/4R 16KB register file under wide operating voltage range between 1V to 0.25V has been designed and implemented in UMC 90nm CMOS technology.

The results shows that register file are operated properly at ultra low voltage. The power consumption and operating frequency are 823uW, 48MHz at 0.5V and 22.9uW, 485 KHz at 0.25V, respectively. The proposed register file will be useful for the future micro-power applications.

Chapter 6 Conclusions

By improving algorithm, architecture, circuit design and process technology, chip performance increases steady. According to ITRS roadmap, memory will occupy most part of chip area in ten years. One of embedded memory is 6T SRAM which is common to be applied to high performance chip. Although future process technology provides chip higher clock speed, lower cost and area, serious PVT variation, production reliability issue, etc. become the significant impact on traditional 6T SRAM.

High-k metal-gate process which is a probable substitute for conventional poly-gate device supplies higher performance for circuit design. However, NBTI/PBTI effect increases Vt value of transistor within usage time and also degrades SRAM performance, like cycle time increasing. Detailed analysis is presented in this thesis. A proposed scheme in this thesis can significantly reduce degradation of SRAM performance by using power switch and change SRAM architecture.

One of methods for improving traditional 6T SRAM is to design a new bit-cell. A new 8T bit-cell which eliminates disturb issue of 6T bit-cell is presented in this thesis.

Read noise margin of new 8T bit-cell has 1.75X improvement compared to tradition 6T bit-cell. Besides, this 8T bit-cell can remain original peripheral circuit of traditional 6T SRAM. Proposed interface circuit is a bridge between traditional SRAM peripheral circuit and new 8T array. Furthermore, interface circuit doesn’t decline performance.

In traditional register file design, designer increases the number of SRAM ports by adding more access transistors. However, stability, cell area, access time and power consumption in this kind design become more serous in future process technology. On the other hands, traditional dual-port, three port SRAM design can’t work under low voltage. A sub-threshold multi-port register file for VLIW DSP is proposed. By using multi-bank, dual-Vt 8T SRAM bit-cell, negative voltage write scheme and improved read footer buffer, proposed register file can work from 1V to 0.25V across various temperature and process corner. The proposed register file is useful for the low-power applications.

Bibliography