Chapter 4 Models of Multi-Bit Sigma-Delta Modulator Power
4.4 Clock driver power and switch power
Cu
V
Cu+ _
(b) (c)
Figure 4.5 (a) Implementation of the integrator and the feedback DAC. (b) To charge the unit capacitance. (c) To discharge the unit capacitance.
4.4 Clock driver power and switch power
Static CMOS logic gates are very power-efficient because they dissipate nearly zero power while idle, so the primary dissipation component is the dynamic dissipation component.
And, the primary dynamic dissipation component is charging and discharging the load capacitance. For much of the history of CMOS design, power was a secondary consideration behind speed and area for many chips. As transistor counts and clock frequencies have increased, power consumption has skyrocketed and now is a primary design constraint.
Begin to review some definitions first. The instantaneous power P t drawn from the ( ) power supply is proportional to the supply current iDD( )t and the supply voltage VDD
( ) DD( ) DD
P t =i t V⋅ . (4.32)
The energy consumed over some time interval T is the integral of the instantaneous power.
And, the energy can be wrote as
0
( )
T
DD DD
E=
∫
i t V dt⋅ . (4.33)The average power over this interval is
0
Considering an ideal inverter and a CMOS inverter with the load capacitor CL are shown in Figure 6 (a) and Figure 6 (b) respectively. Giving a periodic square-wave from the input point is shown in Figure 6 (c). The associated NMOS transistor is ON and the PMOS transistor is OFF when the input signal approach high level voltage at t = . At the same 0− time, the output voltage is 0 volts (GND).
Further, the associated NMOS transistor is OFF and the PMOS transistor is ON when the input signal voltage is changed from high level voltage to low level voltage at t=0. At the same time, the charging current pours into the load capacitor through the channel PMOS transistor, and the output voltage is going to approach high level voltage. At first, the energy of computation is E provided by the power supply is S
However, the energy E which stored up on the load capacitor is C
( ) ( ) ( ) ( )
Therefore, the energy E which dissipated on the PMOS transistor should be equal to the P energy E provided by the power supply to subtract the energy S E stored up on the load C
transistor is ON and the PMOS transistor is OFF. After transformation, the load capacitor will be discharged through the channel of NMOS transistor, and leads to the power dissipation on the NMOS transistor. Consequently, the energy E which dissipated on the NMOS should N be equal to the energy E stored up on the load capacitor, also is C
1 2
N C 2 L DD
E =E = C V⋅ . (4.38)
For this reason, the total energy consumed by the logic gate in one cycle is
(
EP+EN)
=C VLi DD2 . If the input signal frequency of the CMOS inverter is f ,so the dynamic power dissipation PD dyn( ) is2 ( )
D dyn L DD
P = ⋅f C V⋅ . (4.39)
(a) (b)
(c)
Figure 4.6 (a) an ideal inverter for logic level with a load capacitance (b) an ideal CMOS inverter for transistor level with a load capacitance (c) a periodic square-wave for the input.
The switched-capacitor circuits and quantizers require various clock signals. These signals are generated on chip from one external clock signal. The switched-capacitor circuit requires two non-overlapping clocks for sampling and the integration phase. The clock generator with non-overlapping clocks is shown in Figure 2[Gee 02]. From Figure 7, it shows that the clock generator is composed of the logic gates. The primary logic gates which compose of the clock generator are inverters and the NAND gates. Assuming the clock generator has N logic gates, and the capacitance of one capacitor isC Clogic. Under these assumptions the power dissipation of the clock generator can be wrote as
2
clock clock DD
P = ⋅f C ⋅V
2 log
C ic DD
N f C V
= ⋅ ⋅ ⋅ . (4.40)
Figure 4.7 the clock generator with non-overlapping clocks.
Another important component for the power dissipation is offered by CMOS transmitters in the switched-capacitor circuits. The output of the clock generator is connected to the gate of the CMOS switches in the switched-capacitor circuits. The CMOS switch is shown in Figure 4.8. Assuming that the number of the CMOS transmission gate in Sigma-Delta modulator is NS and the gate capacitances of all CMOS transmission gates are Cgate. Under these assumptions the power dissipation of the CMOS switch can be wrote as
2
switch switch DD
P = ⋅f C ⋅V
2
S gate DD
N f C V
= ⋅ ⋅ ⋅ . (4.41)
Figure 4.8 the CMOS switch
Cgate is the capacitance of the gate capacitor in one CMOS switch. The gate of an MOS transistor is a good capacitor. Indeed, its capacitance is necessary to attract charge to invert the channel of the transistor. The gate capacitor can be viewed as a parallel plate capacitor with the gate on top and channel on bottom with the thin oxide dielectric between. From the Table 1[Nei 05], it is clearly to observe that to get the approximation of intrinsic MOS gate capacitance with the CMOS switch. Because the voltage of the gate varies in V and DD GND, the status of the CMOS switch is either cut-off or linear. Consequently, the value of the gate capacitance Cgate can be wrote as
0
Cgate =C
COX W L
= ⋅ ⋅ . (4.42)
where C is the capacitance per unit area of the gate oxide, L is length of the gate, and OX W is width of the gate. C can be wrote as OX
OX
Let RCMOS be remained constant with the input signal level (44) employs the supposition that can be wrote as
After combining the equation (42) with the equation (44), one may derive the results for the gate capacitance Cgate so the gate capacitance Cgate can be wrote as
where L represents the minimum manufacturable length because this results in greatest min speed and lowest power consumption.
logic
C is the value of the gate capacitance in one logic gate. Because the voltage of the
gate varies in V and DD GND with the most logic gates, the status of the MOS of the logic gate is either cut-off or linear. Consequently, the value of the gate capacitance Clogic can be wrote as
logic 2 0
C = C
2COX W L
= ⋅ ⋅ . (4.47)
Table 4.1 Approximation of intrinsic MOS gate capacitance
It may be stated from the above result that the digital power consumption P can be wrote dig as
dig clock switch
P =P +P
=NC⋅ ⋅f Clogic⋅VDD2 +NS⋅ ⋅f Cgate⋅VDD2
The digital power consumption P doesn’t include the logic gates in the quantizer, and dig the dynamic element matching algorithm.