Chapter 2 SUB-HARMONIC MIXER USING 0.18µm CMOS
2.4 Comparison
Table 2.2 shows the comparisons of this work and other recently sub-harmonic
mixer papers. According to the simulation parameters, power dissipation of this work is less than all other circuits, but the linearity is poor with nearly equal conversion voltage gain. We must add some linearity technique to improve the linearity in future work. Because the process condition is falling at the vicinity of SS-corner, the measured results are not good as simulated results. Therefore, bias circuit can be integrated into this sub-harmonic mixer in future tape out to ensure that the
IFp
IFn
10MHz IFp-p = 203.2mV
@RF power = -17dBm LO power = 0dBm
performances are not influenced by process condition. Furthermore, we must base on accurate models and careful simulation to make sure the measurement would close to the simulation.
Table 2.1 Performance Summaries of the sub-harmonic mixer
Specification Simulation Measurement Modify
Supply Voltage (Volt) 1.8 1.8 1.8
LO Power (dBm) -13 0 -3
RF Return Loss (dB) 8.1 9.14 7.42
LO Return Loss (dB) 14.1 6.1 7.3
IF Return Loss (dB) 19.5 N/A 15
LO-to-RF Isolation (dB) >50 23.1 >50 2LO-to-RF Isolation (dB) >50 53 >50
Conversion Power Gain (dB) 1.3 -7.4 -6.76
Conversion Voltage Gain (dB) 8.1 1.12 1.81
P1dB (dBm) -18.6 -14.2 -16.2
IIP3 (dBm) -10.9 -2.3 -6.5
Noise Figure (dB) 11.5 N/A 14.4
Core 2.84 5.74 4.93
Buffer 4.26 3.89 3.55
Power Consumption
(mW) Total 7.1 9.63 8.48
Table 2.2 Comparison of sub-harmonic mixer
[18] [19] [20] This Work
Reference
Specification Sim. Sim. Sim. Sim. Meas.
Supply Voltage (V) 3 3 1.8 1.8
RF Frequency (GHz) 2 5.6 5.6 5.25
Conversion Voltage
Gain (dB) 11.61 8.01 8.05 8.1 1.12
P1dB (dBm) N/A -12 -13.5 -18.6 -14.2
IIP3 (dBm) -13.5 -6.5 0 -10.9 -2.3
Noise Figure (dB) 12 5.96 N/A 11.5 N/A
Mixer Current (mA) 1.71 1.75 2.6 1.58 3.19
Process 0.25µm
CMOS
0.25µm CMOS
0.18µm SiGe
0.18µm CMOS
Chapter 3
C ONCURRENT D UAL -B AND R ECEIVER F RONT -E ND U SING 0.18µm CMOS
Growing market demands of low cost for present WLAN systems push system architecture from multiple-path-multiple-band to concurrent multiple-band type. By employing a sub-harmonic mixer with an LO signal operating at half of RF frequency, a new concurrent dual-band receiver architecture with only one frequency synthesizer for 802.11a/b/g applications is proposed in Chapter 3. The common properties suggest that the two standards can be accommodated in this concurrent dual-band receiver while sharing some of the components. A concurrent dual-band receiver front-end consisting of a differential concurrent dual-band LNA, a Gilbert mixer, and a sub-harmonic mixer is designed and implemented here.
3.1 Review of Receiver Architecture
3.1.1 Superheterodyne Receiver
Most RF communication transceivers manufactured today utilize the superheterodyne receiver architecture, as shown in Fig. 3.1 [21], consisting of a collection of the discrete components with the different technologies such as GaAs,
bipolar, and CMOS.
After receiving RF signal, the signal is downed to baseband by two steps down-conversion, each followed by filtering and amplification. As shown in Fig. 3.1, the first mixer down converts the interested band to IF1. After filtering out the unwanted band, the second mixer down converts the desired channel to IF2.
Fig. 3.1 Superheterodyne receiver
The superheterodyne receiver usually has the superior performance by taking advantage of the high quality (high-Q) discrete components. However, using these discrete components is the contrary to the goal of the high integration by the modern portable communication equipments. The challenge of fully integrating the superheterodyne receiver is to replace the functions implemented by the high performance, high-Q discrete components with the on-chip components. This causes several problems. First, the quality factors of the on-chip passive components are usually much lower than those of the discrete ones. Low-Q passive components will produce the additional noise and the signal losses due to their parasitic resistances.
These low-Q passive components are also difficult to realize the on-chip passive filter to meet the stringent specifications of the image-rejection filter and IF filter. Second, the low-Q inductor also degrades the phase noise of the voltage-controlled oscillator
(VDO). In a conclusion, the superheterodyne receiver is not a suitable solution for integration.
3.1.2 Direct Conversion Receiver
The direct conversion receiver is also named the zero-IF receiver. Obviously, it down-converts the RF signal directly to DC, as shown in Fig. 3.2. Thus, this receiver can eliminate many off-chip filters because it is free from the images. Although the direct conversion receiver allows the high level of integration, it also associates with many problems [22], such as the DC-offsets, even-order distortion, I-Q mismatch, and the flicker noise.
LO RF
ω = ω
ω
ωRF ω
Fig. 3.2 Direct conversion receiver
Due to the isolation between the LO and the RF ports of the mixer is not infinite, large LO signal may couple to the RF port of the mixer. And the LO signal may also radiate to the air and be received by the antenna and input to the RF port of the mixer.
These two effects are called the “LO leakage”. Because the frequencies of the LO and the RF signals are the same, this LO leakage will mix with the LO signal, called the
“self-mixing”, and produces the unexpected DC term. This DC term may corrupt the information near the DC and also may saturate the stages following the mixer. It is not easy to eliminate this DC offset because it is a time-variant term [23]. Furthermore, the down-converted signal is allocated in the vicinity of the DC, the flicker noise
becomes the determinative noise source. It is crucial to process the baseband signal with the low-noise. The easiest solution is using the larger device sizes.
3.1.3 Low-IF Receiver
One integrated low-IF receiver which alleviates the DC-offset problems is shown in Fig. 3.3. The all desired channels are translated to the IF, which is roughly on the order of one or two channel bandwidth. The primary advantage of a low-IF system is free from the DC-offsets.
Unfortunately, the image-rejection becomes the most difficult problem in the low-IF receiver because the image signal is close to the RF signal. Some image-rejection architectures are employed to filter the image signals, such as Hartley and Weaver image-rejection architectures [24]. Another method to suppress the image signal is using the passive polyphase filter [25].
Due to the few building blocks and no DC-offset problem, the low-IF receiver architecture becomes the most appreciate one in the receiver design. Note that IF should be allocated higher than the corner frequency to reduce the flicker noise.
ω
LO Fig. 3.3 Low-IF receiver3.2 Design of Concurrent Dual-Band Receiver
3.2.1 Architecture
By the rapid development and large demand of wireless communication, a fully integration monolithic multi-band radio transceivers are the most significant considerations for communication applications. Wireless LANs provide wideband wireless connectivity between PCs and other consumer electronic devices, allowing access to core networks and other equipment in office and home environments. The commercial WLAN system consists of an RF transceiver together with a base-band and media access controller (MAC) processor. Most of the dual-band receivers now use individual receiving paths shown in Fig. 3.4 but they take large hardware areas.
The hardware cost is considerably high if a dual-band receiver is considered with such scheme. The concurrent dual-band receivers should be taken into account. Fig. 3.5 is the receiver consisting of a dual-band concurrent low-noise amplifier (LNA), two mixers, and a multi-modulus frequency synthesizer. These two mixers are sub-harmonic mixer for 5.25 GHz band and Gilbert mixer for 2.45 GHz band, respectively. On-chip intermediate frequency (IF) filter is required in the system.
Gm-C filters are used for noise bandwidth limiting and anti-aliasing reasons. As shown in Fig. 3.6, the architecture of the proposed dual-band receiver receives signals at the frequency bands of 2.4 GHz to 2.483 GHz in 802.11b/g and 5.15 GHz to 5.35 GHz, 5.725 GHz to 5.825 GHz in 802.11a; it utilizes single path to receive signals from antenna. A concurrent dual-band receiver front-end consisting of a differential concurrent dual-band LNA, a Gilbert mixer, and a sub-harmonic mixer is designed and implemented here.
Fig. 3.4 Conventional architecture of a dual-band receiver
Fig. 3.5 Proposed architecture of the concurrent dual-band receiver
The architecture and frequency plan of the RF transceiver play an important role in the complexity and performance of the overall system. The common choice in transceiver architecture is the traditional superheterodyne and direct conversion.
Direct conversion is a usually choice in a fully integrated design because it avoids the need for an off-chip IF filter and requires only a single frequency synthesizer.
However, it suffers from drawbacks such as local oscillator (LO) leakage and frequency pulling due to the fact that the synthesizer operates at the same frequency as the RF signal [23]. The superheterodyne architecture overcomes many of the disadvantages of direct conversion at the expense of an IF filter and an extra frequency synthesizer [21]. A high performance low-IF dual-band receiver is developed with Gm-C filter. The proposed low-IF receiver front-end combines the
advantages of both the classical IF receiver and the zero-IF receiver, which is an excellent performance and a high degree of integration [26]. Such design also applies this receiving architecture without using external components to achieve circuit integrity and efficiency. Finally the IF is chosen at 10 MHz because of the noise and receiver architecture considerations. Fig. 3.7 shows the frequency plan of this receiver front-end.
Fig. 3.6 Receiving band distribution of WLAN in the range of 2.4~6 GHz
Fig. 3.7 Frequency plan of the concurrent dual-band receiver
3.2.2 Circuit Implementation
The challenge of integrating LNA and mixers comes from the inter-stage design.
In the design procedure we try to match the output matching of differential dual-band LNA and RF input matching of two mixers to the same impedance, for instance, 500Ω parallel with 100pF, rather 50Ω. Large coupling capacitors are added between LNA
and mixers for RF signal coupling and DC isolation. A description of each functional unit is provided as follows:
A. Dual-Band Low-Noise Amplifier
The dual-band LNA is differential inputs in this proposed dual-band receiver front-end. Fig. 3.8 is a schematic of the single-ended dual-band LNA. Two identical single-ended dual-band LNA are paralleled to compose a differential dual-band LNA.
In the single-ended dual-band LNA, the inductively source degeneration consists of a bondwire whose center frequency is tuned to 2.45 GHz and 5.25 GHz. The input matching network and output matching network are the LC tank and LC branch, respectively. As shown in Fig. 3.8, the LC tank is used to resonate the gate impedance and provide the additional lower band gain transfer function. The LC branch introduces a zero in the transfer function of the LNA and performs a notch between 2.45 GHz and 5.25 GHz to improve receiver’s image rejection.The detail analyses of the dual-band single-ended LNA can be found in [27].
Fig. 3.8 Single-ended dual-band LNA B. Sub-Harmonic Mixer for 5.25 GHz Band
The proposed concurrent dual-band receiver front-end adopts sub-harmonic
mixer as shown in Fig. 3.9 in 5.25 GHz band. As described in Chapter 2, the sub-harmonic mixer is based on the classical Gilbert mixer with a switching quad that can conduct on each half cycle of the driving waveform. Different from Chapter 2, this sub-harmonic mixer set input impedance at 500Ω paralleled with 100pF in order to get maximum transfer power gain from LNA. The detail analysis is same as described in Chapter 2.
Fig. 3.9 Sub-harmonic mixer for 5.25 GHz band C. Gilbert Mixer for 2.45 GHz Band
As the conventional receiver, the Gilbert mixer is adopted in 2.45 GHz band in the proposed concurrent dual-band receiver front-end. The sub-harmonic mixer can be served as a Gilbert mixer if LOp port connects with LOn port and LOpj port connects with LOnj port to form two RF inputs and two LO inputs. Therefore, two bands can adopt the same architecture to reduce design complexity. Fig. 3.10 is a Gilbert mixer
which has two RF inputs and two LO inputs. Gilbert mixer has same principles as the sub-harmonic mixer described in Chapter 2.
M1 M2
3.2.3 Circuit Layout
The proposed concurrent dual-band receiver front-end is designed and optimized using 0.18µm 1P6M CMOS technology. All elements are fully integrated on a chip including spiral inductors, MIM capacitors, multi-finger RF MOS transistors, and poly resistors. Similarly, we also take advantage of shielded signal PAD as described previously to reduce coupling noise from the noisy silicon substrate. In order to minimize the phase and the magnitude errors between the differential signal paths, the lengths of signal paths are kept equal as much as possible. To accomplish the more balance, the dummy lines are also added. Furthermore, guard-ring is used to block the
coupling noise between the circuits. The final layout and die photo are shown in Fig.
3.11. The total chip size including the pads is about 1450×1450µm2.
(a) (b) Fig. 3.11 (a) Layout of the concurrent dual-band receiver front-end
(b) Die photo of the concurrent dual-band receiver front-end
3.3 Measurement of Concurrent Dual-Band Receiver
3.3.1 Measurement Consideration
The concurrent dual-band receiver front-end is measured by two PCB boards, 2.45 GHz and 5.25 GHz, rather one PCB board, because of large size off chip passive Balun, too many on-board decoupling capacitors, and complicated DC bias routing.
Fig. 3.12(a) and Fig. 3.12(b) are the PCB layouts of the dual-band receiver front-end, respectively. Because the LO input is quadrature in 5.25 GHz band, the quadrature Balun, which has been mentioned in section 2.3, is required again for 5.25 GHz receiver front-end measurement. There are some comments on PCB boards design.
Firstly the width of RF and LO signal paths on PCB are drawn as 50 Ω-line for impedance matching. Lumped coupling capacitors (1uF) are placed in the RF paths
for dc isolation. To filter out the ineluctable noise and spur from the power supplies we add four lumped decoupling capacitors between each dc voltage and ground, including 100pF, 10nF, 100nF, and 1uF. IF low-pass-filters composed of lumped capacitors and resistors are placed at the IF outputs to depress the high frequency noise. Therefore, the practical PCB test boards of the dual-band receiver front-end are shown in Fig. 3.13(a) and Fig. 3.13(b), respectively. According to measurement setup of Fig. 3.14, we use RFIC measurement system to measure this chip in CIC.
(a) (b) Fig. 3.12 PCB test board layout of concurrent dual-band receiver front-end
for (a) 2.45 GHz band (b) 5.25 GHz band
(a) (b) Fig. 3.13 Practical PCB test board of concurrent dual-band receiver front-end
for (a) 2.45 GHz band (b) 5.25 GHz band
2/4
Quadrature for 5.25 GHz Band Quadrature for 5.25 GHz Band
2/4
Fig. 3.14 Measurement setup of concurrent dual-band receiver front-end
3.3.2 Measurement Results
Upon previous measurement considerations and arrangements, we have made all PCB on-board tests for our design in CIC and our laboratory. In 50Ω measurement system, the measured RF port input return loss of receiver front-end is 15.9 dB and 15.8 dB at 2.45GHz and 5.25GHz, respectively, as shown in Fig. 3.15. The measured LO port input return loss of lower band mixer is 13.4 dB and that of higher band mixer is 13.1 dB, as shown in Fig. 3.16(a) and Fig. 3.16(b), respectively. Fig. 3.17(a) and Fig. 3.17(b) show the measured linearity of the front-end, characterized by the overall RF-to-IF P1dB, are -21 dBm and -15.3 dBm, respectively. Fig. 3.18(a) and Fig.
3.18(b) show the measured dynamic range of the front-end, characterized by the overall RF-to-IF IIP3 for RF signals in two frequency bands, are -4.2 dBm and 4.9 dBm, respectively. Finally, Fig. 3.19 is the IF output waveform measured by oscilloscope. This receiver front-end demonstrates 17.2 dB and 11.8 dB conversion voltage gain at two frequency bands with 28.8 mW power dissipation from a 1.8V supply voltage. The simulated and measured results are summarized in Table 3.1.
Three major factors may depress the gain and increase noise figure of the concurrent dual-band receiver front-end. First, the inter-stage design may be interfered by the parasitic capacitors and resistors, causing the impedance mismatch between the output of differential dual-band LNA and RF input of mixers. Second, the quality factor Q values of the inductors are not good enough due to parasitic resistances. The Q-values of these inductors involved in this work is from 7.08 to 8.27.
The gain and output matching of the concurrent dual-band LNA will be seriously affected by the poor Q-value of inductors. Finally the absence of output buffers at IF output impacts the driving capability of the front-end.
0 1G 2G 3G 4G 5G 6G 7G
Return Loss of RF Port (dB)
Frequency (Hz)
Measurement Simulation
Fig. 3.15 RF port return loss of the receiver front-end
2.0G 2.2G 2.4G 2.6G 2.8G 3.0G
-20
Return Loss of LO Port (dB)
Frequency (Hz)
Measurement Simulation
2.0G 2.2G 2.4G 2.6G 2.8G 3.0G
-20
Return Loss of LO Port (dB)
Frequency (Hz) Measurement
Simulation
(a) (b) Fig. 3.16 LO port return loss of the receiver front-end
for (a) 802.11b/g band (b) 802.11a band
-40 -35 -30 -25 -20 -15 -10 Fig. 3.17 1-dB compression point of the receiver front-end
for (a) 802.11b/g band (b) 802.11a band Fig. 3.18 Third-order-interception point of the receiver front-end
for (a) 802.11b/g band (b) 802.11a band Fig. 3.19 Measured IF output waveform of the receiver front-end
for (a) 802.11b/g band (b) 802.11a band
Table 3.1 Performance summaries of the dual-band receiver front-end 2.45GHz Front-End 5.25GHz Front-End Specification
Sim. Meas. Sim. Meas.
LO Power (dBm) 3 8 -3 7
RF Return Loss (dB) -18.4 15.9 -13.4 15.8 LO Return Loss (dB) -13.2 13.4 -18.3 13.1 Conversion Gain (dB) 14.7 6.0 2.57 -12.0
Voltage Gain (dB) 26.5 17.2 19.9 11.8
Noise Figure (dB) 3.77 7.22 7.28 10.78
P1dB (dBm) -20.6 -21.0 -22.1 -15.3
IIP3 (dBm) -7.8 -4.2 -4.5 4.9
Supply Voltage (V) 1.8
Power Consumption (mW)
Simulation : 17.6 Measurement : 28.8
3.4 Comparison
Table 3.2 shows the comparisons of this work and other recently dual-band receiver front-end papers. Compared with other dual-band receiver front-end this work achieves comparable performances with nearly equal chip area and lower power dissipation under concurrent operation for two frequency bands.
Table 3.2 Comparison of dual-band receiver front-end
*：IF mixer is included
Chapter 4
C ONCLUSIONS A ND F UTURE P ROSPECTS
In this thesis, we start with sub-harmonic mixer design. Then, by employing this sub-harmonic mixer with an LO signal operating at half of RF frequency, we propose a new concurrent dual-band receiver architecture with only one frequency synthesizer for 802.11a/b/g applications. To implement this architecture, we fully integrate concurrent dual-band LNA with sub-harmonic mixer and Gilbert mixer to form concurrent dual-band receiver front-end. All of the simulation performances were finished through Eldo-RF simulator. These two ICs all have been fabricated using 0.18µm CMOS process. And, all measurements were also finished through PCB on-board testing at CIC.
4.1 Conclusions
First, the double-balanced sub-harmonic mixer has been designed and presented in Chapter 2. Because the process condition has been moved toward SS-corner, the measured results are not good as simulated results. The measured conversion voltage gain of the sub-harmonic mixer at RF input of 5.25 GHz with LO input at 2.62 GHz is 1.12 dB. The mixer has a measured IIP3 of -2.3 dBm and an input 1-dB compression
point of -14.2 dBm at 5.25 GHz. The mixer core draws 3.2 mA and the output buffer draws 2.2 mA from a 1.8 V power supply.
The principal challenge in traditional concurrent dual-band receiver arises from the tuning range of frequency synthesizer because of the usage of two Gilbert mixers.
In other words, traditional topology needs two LO signals with large frequency difference. Considering the tuning range of on-chip voltage-controlled oscillator, the only possible solution for the topology may be implementing two frequency synthesizers. To save chip area and power dissipation, a concurrent dual-band receiver
In other words, traditional topology needs two LO signals with large frequency difference. Considering the tuning range of on-chip voltage-controlled oscillator, the only possible solution for the topology may be implementing two frequency synthesizers. To save chip area and power dissipation, a concurrent dual-band receiver