Chapter 3 Proposed Level Shifter Circuit Using
3.6 Comparisons between the Proposed Level Shifter Circuits and Level Shifter
The comparisons of the proposed level shifter circuits and others level shifter circuits including conventional level shifter, NEC’s level shifter, Sharp’s level shifter CML level shifter are given in the output amplitude, circuit configuration, and power consumption in this section. As shown in Table 3-4 the output swing of proposed level shifter circuit_B is larger than that of others level shifter except Sharp’s level shifter circuit. Although high efficiency output swing can be achieved by the Sharp’s level shifter circuit, it is because Sharp’s level shifter circuit the input setting section to magnify input amplitude. However, large power consumption and large layout area still exist in the Sharp’s level shifter circuit.
Because c11 capacitance need over 1uF, that is increase layout area size, and n-channel n11 and p-channel p11 always turn on caused Vdd discharged to Vss leading large power
consumption. In simulation result, the power consumption of proposed level shifter circuits are both smaller than others expect proposed level shifter circuit_A because in the new proposed level shifter ciruit_A utilize T3 TFT to restrain any current flows from the power supply to the Vss. Compare measurement results of proposed level shifter circuits and conventional level shifter circuit is shown Table 3-5. Due to our measurement system does not supply measure AC power consumption, therefore a part of power consumption is
Table 3-4 Comparison of simulation results of the proposed level shifter circuits and others level shifter circuits
Input / Output TFTs Caps. Power consumption DC power Control signals
Table 3-5 Comparison of measurement result of the proposed level shifter circuits and conventional level shifter circuit
4.7 Summary and Conclusions
Novel level shifter circuits using low-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) for the integrated data driver circuits and scan driver circuits of active matrix liquid crystal displays (AMLCD) and active matrix light emitting diodes (AMOLED) have been proposed. In this chapter, novel level shifter circuits have been presented and measured, where level shifter circuits architecture based on three design consideration one is low power others is low input driving and small layout. In proposed level shifter circuit_A composed of two n-type thin film transistors, one p-type thin film transistors, one storage capacitor and one control. signal therefore, a level shifter circuit with simple circuit configuration is achieved. Others level shifter circuit_B and circuit_C are based on circuit_A skeleton so, also keep low power characteristic and extend
Input/Output DC power
consumption Layout area size Control signal
shifter circuit_C 0~5/-9.7~9.6(V) 36.9(pW) 4056 um2 2
added-value like high efficiency and small layout size.
Chapter 4
Summary and Conclusions
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In this thesis, on-glass level shifter driving circuits for LCD are designed and implemented in low temperature poly silicon (LTPS) technology. The driving circuits for LCD are divided into two parts, gate driver and source driver. Gate driver includes shift registers, level shifters, and output buffers. Source driver is composed of shift registers, latches, level shifters, a digital to analog converter, and output buffers. The implement of the on-glass level shifter circuit of scan driver and data driver is the target in this thesis.
In the chapter two, critical issues of several level shifter circuits were discussed and several kinds of level shifter circuits are introduced. The operation principles and configurations of these level shifter circuits were described in detail in this chapter.
We found the greater part of level shifter circuits have high power consumption occurs in the transient period as short-circuit current except NEC’s level shifter circuit.
This current is drawn from the +10V power supply to the -10V Vss through the circuit’s path when input signal is low-to-high or high-to-low. Although NEC’s level shifter circuit have low characteristic but drawback is more control signals are required which increases complexity, moreover sampling capacitor C1 increase layout area size, and if reduce input swing cause have poor output amplitude. In conclusion, the level shifter circuit must have simple configuration, high efficient output amplitude, low power consumption and small layout area characteristics.
In chapter three, new simple level shifter circuits using low-temperature
polycrystalline silicon thin-film transistors (LTPS-TFTs) for the integrated data driver circuits and scan driver circuits of AMLCD and AMOLED is proposed. Moreover, both the simulation and measured results are discueeed in this chapter. In proposed level shifter circuit_A which composed of two n-type thin film transistors, one p-type thin film transistors, one storage capacitor and one control signal therefore, a level shifter circuit with simple circuit configuration is achieved. In proposed level shifter circuit_A consideration of low power consumption it is utilizing n-type TFT (T3) apply for feed back voltage to gate of n-type TFT (T2) and then restrain direct current (DC) power consumption from Vdd to Vss. In proposed level shifter circuit_B in addition to circuit_A skeleton, has input setting bias consists of p-type TFT (T4) and n-type TFT (T5), input setting bias can help circuit_B use low input voltage to obtain high voltage amplitude. Proposed level shifter circuit_C skeleton like circuit_A skeleton except for have not storage capacitor (C1) with one more p-channel TFT (T4) and one control signal (/IN). Because circuit_C have not storage capacitor so can reduce layout area size. Proposed level shifter circuit_B and circuit_C because base on circuit_A skeleton to keep low power consumption characteristic and extend add value like high efficiency and small layout size.
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