Computing Moving Cost

Another heavily operated task in the proposed framework is to compute the moving cost of a metal line, i.e., the number of operations which can make the line observable. To compute the moving cost, we first need to project the target line to each of its upper layers by using a similar way as shown in Figure 3.5, and

17 then search the lines within the projected area on each layer. Those searched lines are the ones which may block the observation of the target line. Next, for each searched blocking line, we project it back to the target line and mark the ends of the projection on the target. Figure 3.7 illustrates this projection process for a case where line a is the target line and line b, c, and d are the blocking lines above a.

F

Figure 3.7: Illustration of the procedure calculating the number of blocking lines for each interval.

In Figure 3.7(a), we first project line b onto line a and mark the left end point and right end point of the projection as value 1 and -1, respectively. By repeating the same action, we then mark the end points for the projection of line c and d as shown in Figure 3.7(b) and Figure 3.7(c). Up to now, line a is divided into several intervals as shown in Figure 3.7(c). Next, we can calculate the number of lines blocking each intervals by summing the marked value from the left to the right.

The summed values are listed on the intervals of line a.

After obtaining the number of lines blocking each intervals, we start to check whether the interval of 0 blocking line can be observable by directly observing it or moving the interval (or part of the interval) to a higher layer right above it. If the interval is already observable, the moving cost of the target line is 0. If the interval can be observable by moving it up, the moving cost is 1. If both cases

18 fail, we need to merge the interval of 0 blocking line with the interval of 1 blocking line, and then check whether the merged interval can be observable by moving all the blocking lines down or plus moving the interval up. If the merged interval can be observable by moving all the blocking lines down and those blocking lines can indeed be feasibly moved down, the moving cost is equal to the number of blocking lines in the merged interval. If the merged interval can be observable by moving all the blocking lines down plus moving itself up, the moving cost is equal to the number of blocking lines plus 1. If both cases fail, we need to merging the interval into the interval with one more blocking line. We repeat the above process until the interval with the most blocking lines is tried. If all above actions fail, the target line is defined as unobservable.

With the help of obtaining the number of blocking lines for each interval, we can systematically find a minimal number of move-up and/or move-down operations to make a target line observable. Such a moving-cost computation avoids the enu-meration and examination of all possible operation combinations, which significantly improves the efficiency of the proposed framework.

Chapter 4

Experimental Results for Maximizing FIB Observable Rate

The experiments in this chapter are conducted based on the same UMC 90nm 9-metal process technology and the same benchmark circuits as used in Table 2.1.

The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17]. Also, we ignore the observation for clock, reset, or scan enable when applying the framework.

4.1 Before and After Applying MFOB

Table 4.1 reports the FIB observable rate based on a 1000nm minimum suf-ficient width of the baseline window and a 1-to-10 edge slope of an FIB hole. The cell-utilization rate is set to 80% to generate the initial layout with SoC Encounter.

Also, dynamic ranking is used in MFOB to determine the order of nets for layout adjustment. In Table 4.1, Column 1 and 2 list the circuit name and its total number of nets, respectively. Column 3 and 4 list the FIB observable rate before and after applying our proposed framework MFOB, respectively. Their difference is listed on Column 5. As the result shows, our proposed framework MFOB can successfully increase the FIB observable rate from 29.50% to 61.67% in average by properly adjusting the initial layout. The improvement in FIB observable rate ranges from 28.85% to 36.34% for different circuits. Note that this average 61.67% of the FIB

19

20 observable rate already exceeds the average FIB observable rate of the benchmark circuits implemented by a 0.18µm process (57.82%) with the same cell utilization rate and FIB technology as shown in Table 2.1.

Table 4.1: Result of applying MFOB.

FIB observable rate (%)

circuit total initial MFOB diff. upper runtime nets (a) (b) (b) - (a) bound (sec) s38417 9296 36.57 69.86 33.30 71.72 52 s38584 5711 28.62 64.96 36.34 67.17 38 s35932 5912 50.84 83.12 32.28 83.85 27

b17 16826 17.86 46.71 28.85 48.90 290

b20 7183 25.62 57.48 31.87 59.36 49

b21 6448 23.47 54.12 30.65 56.54 80

b22 9432 23.56 55.45 31.89 57.96 94

avg. - 29.50 61.67 32.17 63.64

-Column 6 of Table 4.1 lists the upper bound of the observable rate by using MFOB, which is actually the percentage of potentially observable nets estimated based on the initial layout. This upper bound can only be achieved when the layout adjustment for all the potentially observable nets will not interfere with one another, which is not the case in practice. Hence, the true maximum observable rate that can be achieved is limited by the listed upper bound. As Table 4.1 reports, the difference between the observable rate of MFOB and the corresponding upper bound is 1.97%

in average, showing that the observable rate achieved by MFOB is already not far away from the true maximum value. Column 7 of Table 4.1 lists the runtime of MFOB in seconds. The longest runtime is 290 seconds for a circuit with more than 16K nets.

21

4.2 Different Ranking Criteria

In the proposed ranking method for determining the order of nets to be processed, we use the less moving candidates first as the primary criterion and the lower moving cost first as the secondary criterion. Table 4.2 compares the proposed ranking scheme with three different ranking scheme, named as R1, R2, and R3.

R1 uses the more moving candidates first as the primary criterion and the lower moving cost first as the secondary one. R2 uses the less moving candidates first as the primary criterion and the higher moving cost first as the second. R3 uses the more moving candidates first as the primary criterion and the higher moving cost first as the second one, which is completely opposite to the proposed ranking scheme. The FIB observable rates achieved by using the proposed ranking scheme, R1, R2, and R3 are reported on Column 2, 3, 4, and 5 of Table 4.2, respectively.

The other experiment settings are the same as Table 4.1.

Table 4.2: FIB observable rates by using different ranking criteria.

FIB observable rate (%)

circuit proposed R1 R2 R3

s38417 69.86 69.34 69.74 69.24 s38584 64.96 64.48 64.96 64.48 s35932 83.12 82.83 83.11 82.82 b17 46.71 45.87 46.67 45.83 b20 57.48 57.06 57.48 57.03 b21 54.12 53.34 54.06 53.29 b22 55.45 54.65 55.38 54.62 avg. 61.67 61.08 61.63 61.04

As the result shows, the proposed ranking scheme can achieve higher observ-able rate than any of the other three ranking schemes for every benchmark circuit.

On the other hand, the ranking scheme completely opposite to our proposed one (R3) achieves the lowest observable rate for every benchmark circuit as well. This

22 result demonstrates that the ranking criteria used in our proposed framework are indeed critical and helpful for maximizing the observable rate.

4.3 Dynamic Ranking vs. Static Ranking

In the above experiments, we utilize the dynamic ranking, which updates the newest ranking of the nets once after every layout adjustment and consumes more runtime. In Table 4.3, we compare the dynamic ranking with the static one, i.e., using only the net ranking obtained from the initial layout to determine the order of nets to be processed. As the result shows, the observable rate achieved by the dynamic ranking is indeed higher than that by the static ranking for each benchmark circuit, and their average difference is 0.21%. On the other hand, the runtime of using the dynamic ranking is in average 12% higher than that of the static ranking, which is affordable trade-off for using the dynamic ranking.

Table 4.3: Comparison between the dynamic ranking and static ranking.

FIB observable rate runtime

circuit dynamic static diff. dynamic static ratio (a) (b) (a) - (b) (c) (d) (d) / (c)

s38417 69.86 69.64 0.22 52 47 0.89

s38584 64.96 64.64 0.31 38 34 0.90

s35932 83.12 82.98 0.14 27 24 0.91

b17 46.71 46.55 0.16 290 242 0.83

b20 57.48 57.29 0.20 49 43 0.87

b21 54.12 53.86 0.27 50 44 0.88

b22 55.45 55.26 0.18 94 82 0.87

avg. 61.67 61.46 0.21 - - 0.88

4.4 Different Cell-utilization Rate

The observable rate of a design’s initial layout is affected by the cell-utilization rate set to the APR tool. A higher cell-utilization rate will result in smaller area

23 overhead and higher layout density, which in general leads to a lower FIB observable rate since denser metal lines may easily block the FIB observation of one another.

In practice, a layout with 80% cell-utilization rate is already an acceptable one. A layout with 90% cell-utilization would be a really high quality one and is difficult to obtain for large industrial designs.

Table 4.4 reports the observable rate of the initial layout generated by setting the cell-utilization rate to 80%, 85%, and 90%, as well as its corresponding observable rate after applying MFOB. As the result shows, a higher cell-utilization rate always leads to a lower observable rate for the initial layout. Also, the observable-rate improvement achieved by MFOB is 32.17% (61.67-29.50), 31.53% (59.13-27.60), and 32.03% (57.75-25.72) for a 80%, 85%, and 90% cell-utilization rate, respectively.

This result demonstrates that MFOB can still effectively improve the FIB observable rate for the layouts with different cell utilization rates.

Table 4.4: FIB observable rates based on the initial layout with different cell-utilization rates

cell-utilization rates

circuit 80 85 90

initial MFOB initial MFOB initial MFOB s38417 36.57 69.86 34.04 67.76 32.95 67.55 s38584 28.62 64.96 27.20 64.90 25.12 62.82 s35932 50.84 83.12 47.42 80.13 43.15 77.87 b17 17.86 46.71 16.64 43.80 16.11 42.51 b20 25.62 57.48 23.49 53.00 22.67 50.54 b21 23.47 54.12 23.34 52.40 19.61 50.93 b22 23.56 55.45 21.03 51.91 20.45 52.05 avg. 29.50 61.67 27.60 59.13 25.72 57.75

24

4.5 Impact on Circuit’s Timing

Even though a move-up or move-down operation may add extra vias to a net, which increases its resistance, the circuit’s timing after applying our proposed framework usually becomes faster than its initial layout. Table 4.5 lists the longest path delay before and after applying MFOB, which is reported by a commercial timing analysis tool [18] with the result of layout RC extraction. As the result shows, the timing after applying MFOB can indeed become faster than the timing of its initial layout for every benchmark circuit. Also, every modified layout passes the connection checking and equivalence checking.

Table 4.5: The longest-path delay before and after applying MFOB.

circuit longest path (ns)

This faster timing of the modified layout results from the following two rea-sons. First, the long delay of a critical path usually results from the large coupling capacitance affected by the long paralleled metal lines in its neighborhood. Fortu-nately, the operations used in our framework often move only a portion of a metal line to another layer, which can reduce the overlapping length of the paralleled lines and in turn reduce the coupling capacitance. Second, for most CMOS technolo-gies, the unit-length capacitance of the metal on a higher layer is smaller than that on a lower layer. In our framework, a move-up operation is performed more often than a move-down operation, meaning that the metal used on higher layers becomes

25 more after the layout adjustment. As a result, the overall metal capacitance usually decreases and so does the timing of the circuit.

Table 4.6: Timing comparison between MFOB with and without locking the top 50 longest paths.

critical path avg. timing diff. FIB observable circuit (ns) for top 50 paths (%) rate (%)

no lock lock no lock lock no lock lock s38417 1.09486 1.09485 -0.07770 -0.07887 69.86 67.22 s38584 1.49481 1.49698 -0.10887 -0.10907 64.96 6438 s35932 1.79595 1.79602 -0.07860 -0.07907 83.12 82.78 b17 6.71904 6.71894 -0.10497 -0.10731 46.71 45.97 b20 4.25394 4.25793 -0.12390 -0.10775 57.48 54.40 b21 4.31786 4.31997 -0.10199 -0.05618 54.12 51.74 b22 5.39174 5.39194 -0.12210 -0.13058 55.45 53.55

avg. - - -0.10259 -0.09555 61.67 60.01

MFOB has a feature which can maximize the observable rate while locking the layout of the given paths, meaning that MFOB can only perform move-up and move-down operations to the metal lines not on the given paths. Table 4.6 reports the result of applying MFOB with the top 50 longest paths locked. These top 50 longest paths are also reported from the timing analysis tool [18] based on the initial layout. In Table 4.6, Column 2 and 3 first shows that the delay of the most critical path without locking the 50 paths is always smaller than that with locking the 50 paths, but the difference is very limited. Column 4 and 5 calculates the average difference of the 50 paths’ delay between the modified layout and initial layout after applying MFOB without and with locking the 50 paths, respectively. The result shows that MFOB without locking the 50 paths can reduce the average path delay for the initial layout more than that with locking the paths. We also found that the above situation actually happens to each of the 50 longest path without exception.

This result confirms that the coupling capacitance can be reduced by moving only a portion of a metal line to another layer and in turn reduce the delay of the 50

26 longest paths even though the layout of these 50 longest paths is not changed. In addition, Column 6 and 7 show that the FIB observable achieved by not locking the 50 paths is in average 1.66% higher than that locking the 50 paths.

Chapter 5

Future Work: Maximizing FIB Repairable Rate

The above chapters, we have introduced how to maximize the number of nets being observable by FIB probing for a given layout. In this chapter, we would like to further discuss the differences that the proposed framework may need to make for maximizing the number of nets being repairable by FIB circuit editing. To repair a signal, two actions need to be performed. The first action is to reconnect the cut signal to a new one, which is done by digging an FIB hole onto each of the target line and the line connecting to, filling metal into the two holes, and connecting them together. The second action is to cut the connection of the original signal source, which is done by digging an FIB hole, breaking through the target metal line and then filling the hole with insulator. Figure 5.1 illustrates an example of cutting the signal a and reconnect it to a new signal b. Thus, in order to successfully apply the FIB circuit editing to repair a signal, we need to dug two FIB holes to the metal lines of the signal, one for cutting the original connection and the other for reconnecting.

Note that the cutting hole and the reconnecting hole can physically locate next to each other without interfering.

As a result, when building the framework for maximizing the FIB repairable rate, we need to check not only whether an FIB hole can successfully land onto a metal line (as in MFOB) but also how many FIB holes can successfully land onto the metal line. Also, when using the FIB circuit editing, cutting different locations

27

28

Figure 5.1: An example of using FIB circuit editing to repair a signal.

of a net will result in different repaired functions. For example, cutting the stem of a multiple fanout net will function different from cutting a branch of the same net. Thus, the unit of calculating the FIB repairable rate is different from the FIB observable rate as well.

Chapter 6 Conclusions

In this thesis, we have proposed a DFD framework, named MFOB, which can increase the FIB observable rate by using a greedy-based algorithm to iteratively adjust the layout for a selected signal. An effective ranking scheme has also been developed to generate a proper order of signals for layout adjustment and maximize the resulting observable rate. A series of experiments have demonstrated that the targeted observable rate of the initial layout can be significantly increased without violating any design rule. Meanwhile, the adjusted layout can remain the same size and its timing can even become slightly better. Its runtime is also within a reasonable range for a software dealing with the complete layout database. In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.

29

Bibliography

[1] M. Abramovici, P. Bradley, K. Dwarakanath, P. Levin, G. Memmi, and D. Miller,

”A Reconfigurable Design-for-Debug Infrastructure for SoCs”, Design Automation Conference, pp. 7-12, 2006.

[2] R. Goering, ”Post-Silicon Debugging Worth a Second Look”, EETimes, Feb. 05, 2007.

[3] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing, Kluwer, Boston, 2000.

[4] E. Anis and N. Nicolico, ”On Using Lossless Compression of Debug Data in Em-bedded Logic Analyis”, International Test Conference, pp. 1-10, 2007.

[5] E. Anis and N. Nicolico, ”Low Cost Debug Architecture using Lossy Compression for Silicon Debug”, Design Automation, and Test in Europe, pp. 1-6, 2007.

[6] J.-S. Yang and Nur A. Touba, ”Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture”, VLSI Tset Symposium, pp.

345-351, 2008.

[7] C. Shawn, C. C. Tsao, and T. R. Lundquist, ”Measuring back-side voltage of an integrated circuit”, U.S. Patent 6,872,581 B2, 2005.

[8] W.-M. Yee, M. Paniicia, T. Eiles, and V. Rao, ”Laser Voltage Probe (LVP): a Novel Optical Probing Technology for Flip-Chip Package Microprocessors”, Internation Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 15-20, 1999.

[9] M. T. Abramo and L. L. Hahn, ”The Application of Advanced Techniques for Complex Focused-Ion-Beam Device Modification”, Microelectronics Reliability, Vol.

36, Issues 11-12, pp. 1775-1778, 1996.

[10] C. G. Talbot, M. Park, N. Richardson, P. Alto, and D. Masnaghetti, ”IC Modifica-tion with Foucused Ion Beam System”, U.S. patent 5,140,164, 1992.

[11] D. C. Shaver and B. W. Ward, ”Integrated Circuit Diagnosis Using Foucused Ion Beams”, Journal of Vacuum Science & Technology B; Microelectronics and Nanometer Structures, Vol. 4, Issuse 1, pp. 185-188, 1986.

30

31 [12] R. Schlangen, R. Leihkauf, U. Kerst, C. Boit, and B. Kruger, ”Functional IC

Anal-ysis Through Chip Backside With Nano Scale Resolution - E-Beam Probing in FIB Trenches to STI Level”, International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp. 35-38, 2007.

[13] J. Nonaka, ”Design for Failure Analysis by using LVP Measurement Elements”, Semi Technology Symposium, pp45-48, 2003.

[14] J. Nonaka, T. Ishiyama, and K. Shigeta, ”Design for Failure Analysis inserting Replacement-type Observation Points for LVP”, International Testing Conference, pp. 1-10, 2009.

[15] Y.-R. Wu, S.-Y. Kao, and S.-A. Hwang, ”Minimizing ECO routing for FIB”, VLSI Design Automation and Test, pp. 351-354, 2010.

[16] FEI Company, ”Focused Ion Beam Technology, Capabilites and Applications”, http://www.fei.com.

[17] Cadence, ”Encounder User Guide,” version 8.1.2, 2009.^R [18] Synopsys, PrimeTime, version B-2008.12-SP3-2, 2009.