Chapter 3 The MIPS32™ Instruction Set
C. cond.fmt
Table 3-13 FPU Convert Instructions
Mnemonic Instruction
CEIL.W.fmt Floating Point Ceiling Convert to Word Fixed Point CVT.D.fmt Floating Point Convert to Double Floating Point CVT.S.fmt Floating Point Convert to Single Floating Point CVT.W.fmt Floating Point Convert to Word Fixed Point FLOOR.W.fmt Floating Point Floor Convert to Word Fixed Point ROUND.W.fmt Floating Point Round to Word Fixed Point TRUNC.W.fmt Floating Point Truncate to Word Fixed Point
3.2 Alphabetical List of Instructions
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Table 3-14 FPU Load, Store, and Memory Control Instructions
Mnemonic Instruction
LDC1 Load Doubleword to Floating Point LWC1 Load Word to Floating Point
SDC1 Store Doubleword from Floating Point SWC1 Store Word from Floating Point
Table 3-15 FPU Move Instructions
Mnemonic Instruction
CFC1 Move Control Word from Floating Point CTC1 Move Control Word to Floating Point MFC1 Move Word from Floating Point MOV.fmt Floating Point Move
MOVF.fmt Floating Point Move Conditional on Floating Point False MOVN.fmt Floating Point Move Conditional on Not Zero
MOVT.fmt Floating Point Move Conditional on Floating Point True MOVZ.fmt Floating Point Move Conditional on Zero
MTC1 Move Word to Floating Point
Table 3-16 Obsoletea FPU Branch Instructions
a. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture.
Mnemonic Instruction
BC1FL Branch on FP False Likely BC1TL Branch on FP True Likely
Table 3-17 Coprocessor Branch Instructions
Mnemonic Instruction
BC2F Branch on COP2 False
BC2T Branch on COP2 True
Table 3-18 Coprocessor Execute Instructions
Mnemonic Instruction
COP2 Coprocessor Operation to Coprocessor 2
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Table 3-19 Coprocessor Load and Store Instructions
Mnemonic Instruction
LDC2 Load Doubleword to Coprocessor 2 LWC2 Load Word to Coprocessor 2
SDC2 Store Doubleword from Coprocessor 2 SWC2 Store Word from Coprocessor 2
Table 3-20 Coprocessor Move Instructions
Mnemonic Instruction
CFC2 Move Control Word from Coprocessor 2 CTC2 Move Control Word to Coprocessor 2 MFC2 Move Word from Coprocessor 2 MTC2 Move Word to Coprocessor 2
Table 3-21 Obsoletea Coprocessor Branch Instructions
a. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture.
Mnemonic Instruction
BC2FL Branch on COP2 False Likely BC2TL Branch on COP2 True Likely
Table 3-22 Privileged Instructions
Mnemonic Instruction
CACHE Perform Cache Operation
ERET Exception Return
MFC0 Move from Coprocessor 0 MTC0 Move to Coprocessor 0 TLBP Probe TLB for Matching Entry TLBR Read Indexed TLB Entry TLBWI Write Indexed TLB Entry TLBWR Write Random TLB Entry
WAIT Enter Standby Mode
3.2 Alphabetical List of Instructions
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Table 3-23 EJTAG Instructions
Mnemonic Instruction
DERET Debug Exception Return SDBBP Software Debug Breakpoint
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ABS.fmt
Format: ABS.S fd, fs MIPS32 (MIPS I)
ABS.D fd, fs MIPS32 (MIPS I)
Purpose:
To compute the absolute value of an FP value Description:fd ← abs(fs)
The absolute value of the value in FPR fs is placed in FPR fd. The operand and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.
This operation is arithmetic; a NaN operand signals invalid operation.
Restrictions:
The fields fs and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE-DICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand FPR becomes UNPREDICTABLE.
Operation:
StoreFPR(fd, fmt, AbsoluteValue(ValueFPR(fs, fmt)))
Exceptions:
Coprocessor Unusable, Reserved Instruction Floating Point Exceptions:
Unimplemented Operation, Invalid Operation
31 26 25 21 20 16 15 11 10 6 5 0
Floating Point Absolute Value ABS.fmt
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ADD
Format: ADD rd, rs, rt MIPS32 (MIPS I)
Purpose:
To add 32-bit integers. If an overflow occurs, then trap.
Description:rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rd.
Restrictions:
ADDU performs the same arithmetic operation but does not trap on overflow.
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL
000000 rs rt rd
0
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ADD.fmt
Format: ADD.S fd, fs, ft MIPS32 (MIPS I)
ADD.D fd, fs, ft MIPS32 (MIPS I)
Purpose:
To add floating point values Description:fd ← fs + ft
The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.
Restrictions:
The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE-DICTABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.
Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) +fmt ValueFPR(ft, fmt))
Exceptions:
Coprocessor Unusable, Reserved Instruction Floating Point Exceptions:
Unimplemented Operation, Invalid Operation, Inexact, Overflow, Underflow
31 26 25 21 20 16 15 11 10 6 5 0
COP1
010001 fmt ft fs fd
ADD 000000
6 5 5 5 5 6
Floating Point Add ADD.fmt
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ADDI
Format: ADDI rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To add a constant to a 32-bit integer. If overflow occurs, then trap.
Description:rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rt.
Restrictions:
None Operation:
temp ← (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate) if temp32 ≠ temp31 then
SignalException(IntegerOverflow) else
GPR[rt] ← temp endif
Exceptions:
Integer Overflow Programming Notes:
ADDIU performs the same arithmetic operation but does not trap on overflow.
31 26 25 21 20 16 15 0
ADDI
001000 rs rt immediate
6 5 5 16
Add Immediate Word ADDI
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ADDIU
Format: ADDIU rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To add a constant to a 32-bit integer Description:rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rt.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None Operation:
temp ← GPR[rs] + sign_extend(immediate) GPR[rt]← temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith-metic environments that ignore overflow, such as C language aritharith-metic.
31 26 25 21 20 16 15 0
ADDIU
001001 rs rt immediate
6 5 5 16
Add Immediate Unsigned Word ADDIU
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ADDU
Format: ADDU rd, rs, rt MIPS32 (MIPS I)
Purpose:
To add 32-bit integers
Description:rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rd.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None Operation:
temp ← GPR[rs] + GPR[rt]
GPR[rd] ← temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith-metic environments that ignore overflow, such as C language aritharith-metic.
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL
000000 rs rt rd
0 00000
ADDU 100001
6 5 5 5 5 6
Add Unsigned Word ADDU
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AND
Format: AND rd, rs, rt MIPS32 (MIPS I)
Purpose:
To do a bitwise logical AND Description:rd ← rs AND rt
The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is placed into GPR rd.
Restrictions:
None Operation:
GPR[rd] ← GPR[rs] and GPR[rt]
Exceptions:
None
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL
000000 rs rt rd
0 00000
AND 100100
6 5 5 5 5 6
And AND
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ANDI
Format: ANDI rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To do a bitwise logical AND with a constant Description:rt ← rs AND immediate
The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical AND operation. The result is placed into GPR rt.
Restrictions:
None Operation:
GPR[rt] ← GPR[rs] and zero_extend(immediate)
Exceptions:
None
31 26 25 21 20 16 15 0
ANDI
001100 rs rt immediate
6 5 5 16
And Immediate ANDI
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B
Format: B offset Assembly Idiom
Purpose:
To do an unconditional branch Description:branch
B offset is the assembly idiom used to denote an unconditional branch. The actual instruction is interpreted by the hardware as BEQ r0, r0, offset.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) I+1: PC ← PC + target_offset
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is±128 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
31 26 25 21 20 16 15 0
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BAL
Format: BAL rs, offset Assembly Idiom
Purpose:
To do an unconditional PC-relative procedure call Description:procedure_call
BAL offset is the assembly idiom used to denote an unconditional branch. The actual instruction is iterpreted by the hardware as BGEZAL r0, offset.
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Operation:
I: target_offset ← sign_extend(offset || 02) GPR[31] ← PC + 8
I+1: PC ← PC + target_offset
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is±128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
31 26 25 21 20 16 15 0
Branch and Link BAL
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BC1F
Format: BC1F offset (cc = 0 implied) MIPS32 (MIPS I)
BC1F cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and do a PC-relative conditional branch Description:if cc = 0 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con-dition code bit CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition ← FPConditionCode(cc) = 0 target_offset ← (offset15)GPRLEN-(16+2)
|| offset || 02 I+1: if condition then
PC ← PC + target_offset
Branch on FP False BC1F
42 MIPS32™ Architecture For Programmers Volume II, Revision 0.95 Exceptions:
Coprocessor Unusable, Reserved Instruction Floating Point Exceptions:
Unimplemented Operation Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is±128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.
Branch on FP False (cont.) BC1F
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BC1FL
Format: BC1FL offset (cc = 0 implied) MIPS32 (MIPS II)
BC1FL cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and make a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
Description:if cc = 0 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con-dition Code bit CC is false (0), the program branches to the effective target address after the instruction in the delay slot is executed. If the branch is not taken, the instruction in the delay slot is not executed.
An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition ← FPConditionCode(cc) = 0 target_offset ← (offset15)GPRLEN-(16+2)
|| offset || 02 I+1: if condition then
PC ← PC + target_offset else
Branch on FP False Likely BC1FL
44 MIPS32™ Architecture For Programmers Volume II, Revision 0.95 Exceptions:
Coprocessor Unusable, Reserved Instruction Floating Point Exceptions:
Unimplemented Operation Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is±128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture.
Some implementations always predict the branch will be taken, so there is a significant penalty if the branch is not taken. Software should only use this instruction when there is a very high probability (98% or more) that the branch will be taken. If the branch is not likely to be taken or if the probability of a taken branch is unknown, software is encouraged to use the BC1F instruction instead.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
In the MIPS II andIII architectionrsthere must be at least one instruction between the compare instruction that sets a condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.
Branch on FP False Likely (cont.) BC1FL
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BC1T
Format: BC1T offset (cc = 0 implied) MIPS32 (MIPS I)
BC1T cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and do a PC-relative conditional branch Description:if cc = 1 then branch
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP con-dition code bit CC is true (1), the program branches to the effective target address after the instruction in the delay slot is executed. An FP condition code is set by the FP compare instruction, C.cond.fmt.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
Operation:
This operation specification is for the general Branch On Condition operation with the tf (true/false) and nd (nullify delay slot) fields as variables. The individual instructions BC1F, BC1FL, BC1T, and BC1TL have specific values for tf and nd.
I: condition ← FPConditionCode(cc) = 1 target_offset ← (offset15)GPRLEN-(16+2)
|| offset || 02 I+1: if condition then
PC ← PC + target_offset
Branch on FP True BC1T
46 MIPS32™ Architecture For Programmers Volume II, Revision 0.95 Exceptions:
Coprocessor Unusable, Reserved Instruction Floating Point Exceptions:
Unimplemented Operation Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is±128 KBytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
Historical Information:
The MIPS I architecture defines a single floating point condition code, implemented as the coprocessor 1 condition signal (Cp1Cond) and the C bit in the FP Control/Status register. MIPS I, II, and III architectures must have the CC field set to 0, which is implied by the first format in the “Format” section.
The MIPS IV and MIPS32 architectures add seven more Condition Code bits to the original condition code 0. FP compare and conditional branch instructions specify the Condition Code bit to set or test. Both assembler formats are valid for MIPS IV and MIPS32.
In the MIPS I, II, and III architectures there must be at least one instruction between the compare instruction that sets the condition code and the branch instruction that tests it. Hardware does not detect a violation of this restriction.
Branch on FP True (cont.) BC1T
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BC1TL
Format: BC1TL offset (cc = 0 implied) MIPS32 (MIPS II)
BC1TL cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and do a PC-relative conditional branch; execute the instruction in the delay slot only if the branch is taken.
Description:if cc = 1 then branch_likely
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con-dition Code bit CC is true (1), the program branches to the effective target address after the instruction in the delay
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself) in the branch delay slot to form a PC-relative effective target address. If the FP Con-dition Code bit CC is true (1), the program branches to the effective target address after the instruction in the delay