Chapter 2 Guide to the Instruction Set
2.4 FPU Instructions
In the detailed description of each FPU instruction, all variable subfields in an instruction format (such as fs, ft, immediate, and so on) are shown in lowercase. The instruction name (such as ADD, SUB, and so on) is shown in uppercase.
For the sake of clarity, an alias is sometimes used for a variable subfield in the formats of specific instructions. For example, rs=base in the format for load and store instructions. Such an alias is always lowercase since it refers to a variable subfield.
Bit encodings for mnemonics are given in Volume I, in the chapters describing the CPU, FPU, MDMX, and MIPS16 instructions.
See Section 2.3 , "Op and Function Subfield Notation" on page 20 for a description of the op and function subfields.
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The MIPS32™ Instruction Set
3.1 Compliance and Subsetting
To be compliant with the MIPS32 Architecture, designs must implement a set of required features, as described in this document set. To allow flexibility in implementations, the MIPS32 Architecture does provide subsetting rules. An implementation that follows these rules is compliant with the MIPS32 Architecture as long as it adheres strictly to the rules, and fully implements the remaining instructions.
The instruction set subsetting rules are as follows:
• All CPU instructions must be implemented - no subsetting is allowed.
• The FPU and related support instructions, including the MOVF and MOVT CPU instructions, may be omitted.
Software may determine if an FPU is implemented by checking the state of the FP bit in the Config1 CP0 register. If the FPU is implemented, it must include S, D, and W formats, operate instructions, and all supporting instructions.
Software may determine which FPU data types are implemented by checking the appropriate bit in the FIR CP1 register. The following allowable FPU subsets are compliant with the MIPS32 architecture:
– No FPU
– FPU with S, D, and W formats and all supporting instructions –
• Coprocessor 2 is optional and may be omitted. Software may determine if Coprocessor 2 is implemented by checking the state of the C2 bit in the Config1 CP0 register. If Coprocessor 2 is implemented, the Coprocessor 2 interface instructions (BC2, CFC2, COP2, CTC2, LDC2, LWC2, MFC2, MTC2, SDC2, and SWC2) may be omitted on an instruction by instruction basis.
• Instruction fields that are marked “Reserved” or shown as “0” in the description of that field are reserved for future use by the architecture and are not available to implementations. Implementations may only use those fields that are explicitly reserved for implementation dependent use.
• Supported ASEs are optional and may be subsetted out. If most cases, software may determine if a supported ASE is implemented by checking the appropriate bit in the Config1 or Config3 CP0 register. If they are implemented, they must implement the entire ISA applicable to the component, or implement subsets that are approved by the ASE specifications.
• If any instruction is subsetted out based on the rules above, an attempt to execute that instruction must cause the appropriate exception (typically Reserved Instruction or Coprocessor Unusable).
Supersetting of the MIPS32 ISA is only allowed by adding functions to the SPECIAL2 major opcode or by adding instructions to support Coprocessor 2.
3.2 Alphabetical List of Instructions
Table 3-1throughTable 3-23provide a list of instructions grouped by category. Individual instruction descriptions follow the tables, arranged in alphabetical order.
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Table 3-1 CPU Arithmetic Instructions
Mnemonic Instruction
ADD Add Word
ADDI Add Immediate Word
ADDIU Add Immediate Unsigned Word
ADDU Add Unsigned Word
CLO Count Leading Ones in Word CLZ Count Leading Zeros in Word
DIV Divide Word
DIVU Divide Unsigned Word
MADD Multiply and Add Word to Hi, Lo
MADDU Multiply and Add Unsigned Word to Hi, Lo MSUB Multiply and Subtract Word to Hi, Lo
MSUBU Multiply and Subtract Unsigned Word to Hi, Lo
MUL Multiply Word to GPR
MULT Multiply Word
MULTU Multiply Unsigned Word
SLT Set on Less Than
SLTI Set on Less Than Immediate
SLTIU Set on Less Than Immediate Unsigned SLTU Set on Less Than Unsigned
SUB Subtract Word
SUBU Subtract Unsigned Word
Table 3-2 CPU Branch and Jump Instructions
Mnemonic Instruction
B Unconditional Branch
BAL Branch and Link
BEQ Branch on Equal
BGEZ Branch on Greater Than or Equal to Zero
BGEZAL Branch on Greater Than or Equal to Zero and Link BGTZ Branch on Greater Than Zero
BLEZ Branch on Less Than or Equal to Zero BLTZ Branch on Less Than Zero
3.2 Alphabetical List of Instructions
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BLTZAL Branch on Less Than Zero and Link
BNE Branch on Not Equal
J Jump
JAL Jump and Link
JALR Jump and Link Register
JR Jump Register
Table 3-3 CPU Instruction Control Instructions
Mnemonic Instruction
NOP No Operation
SSNOP Superscalar No Operation
Table 3-4 CPU Load, Store, and Memory Control Instructions
Mnemonic Instruction
LB Load Byte
LBU Load Byte Unsigned
LH Load Halfword
LHU Load Halfword Unsigned
LL Load Linked Word
LW Load Word
LWL Load Word Left
LWR Load Word Right
PREF Prefetch
SB Store Byte
SC Store Conditional Word
SD Store Doubleword
SH Store Halfword
SW Store Word
SWL Store Word Left
SWR Store Word Right
SYNC Synchronize Shared Memory
Table 3-2 CPU Branch and Jump Instructions
Mnemonic Instruction
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Table 3-5 CPU Logical Instructions
Mnemonic Instruction
AND And
ANDI And Immediate
LUI Load Upper Immediate
NOR Not Or
OR Or
ORI Or Immediate
XOR Exclusive Or
XORI Exclusive Or Immediate
Table 3-6 CPU Move Instructions
Mnemonic Instruction
MFHI Move From HI Register MFLO Move From LO Register
MOVF Move Conditional on Floating Point False MOVN Move Conditional on Not Zero
MOVT Move Conditional on Floating Point True MOVZ Move Conditional on Zero
MTHI Move To HI Register
MTLO Move To LO Register
Table 3-7 CPU Shift Instructions
Mnemonic Instruction
SLL Shift Word Left Logical SLLV Shift Word Left Logical Variable SRA Shift Word Right Arithmetic SRAV Shift Word Right Arithmetic Variable SRL Shift Word Right Logical
SRLV Shift Word Right Logical Variable
3.2 Alphabetical List of Instructions
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Table 3-8 CPU Trap Instructions
Mnemonic Instruction
BREAK Breakpoint
SYSCALL System Call
TEQ Trap if Equal
TEQI Trap if Equal Immediate TGE Trap if Greater or Equal
TGEI Trap if Greater of Equal Immediate
TGEIU Trap if Greater or Equal Immediate Unsigned TGEU Trap if Greater or Equal Unsigned
TLT Trap if Less Than
TLTI Trap if Less Than Immediate
TLTIU Trap if Less Than Immediate Unsigned TLTU Trap if Less Than Unsigned
TNE Trap if Not Equal
TNEI Trap if Not Equal Immediate
Table 3-9 Obsoletea CPU Branch Instructions
a. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture.
Mnemonic Instruction
BEQL Branch on Equal Likely
BGEZALL Branch on Greater Than or Equal to Zero and Link Likely BGEZL Branch on Greater Than or Equal to Zero Likely
BGTZL Branch on Greater Than Zero Likely BLEZL Branch on Less Than or Equal to Zero Likely BLTZALL Branch on Less Than Zero and Link Likely BLTZL Branch on Less Than Zero Likely
BNEL Branch on Not Equal Likely
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Table 3-10 FPU Arithmetic Instructions
Mnemonic Instruction
ABS.fmt Floating Point Absolute Value ADD.fmt Floating Point Add
DIV.fmt Floating Point Divide MADD.fmt Floating Point Multiply Add MSUB.fmt Floating Point Multiply Subtract MUL.fmt Floating Point Multiply NEG.fmt Floating Point Negate
NMADD.fmt Floating Point Negative Multiply Add NMSUB.fmt Floating Point Negative Multiply Subtract RECIP.fmt Reciprocal Approximation
RSQRT.fmt Reciprocal Square Root Approximation SQRT Floating Point Square Root
SUB.fmt Floating Point Subtract
Table 3-11 FPU Branch Instructions
Mnemonic Instruction
BC1F Branch on FP False
BC1T Branch on FP True
Table 3-12 FPU Compare Instructions
Mnemonic Instruction
C.cond.fmt Floating Point Compare
Table 3-13 FPU Convert Instructions
Mnemonic Instruction
CEIL.W.fmt Floating Point Ceiling Convert to Word Fixed Point CVT.D.fmt Floating Point Convert to Double Floating Point CVT.S.fmt Floating Point Convert to Single Floating Point CVT.W.fmt Floating Point Convert to Word Fixed Point FLOOR.W.fmt Floating Point Floor Convert to Word Fixed Point ROUND.W.fmt Floating Point Round to Word Fixed Point TRUNC.W.fmt Floating Point Truncate to Word Fixed Point
3.2 Alphabetical List of Instructions
MIPS32™ Architecture For Programmers Volume II, Revision 0.95 27
Table 3-14 FPU Load, Store, and Memory Control Instructions
Mnemonic Instruction
LDC1 Load Doubleword to Floating Point LWC1 Load Word to Floating Point
SDC1 Store Doubleword from Floating Point SWC1 Store Word from Floating Point
Table 3-15 FPU Move Instructions
Mnemonic Instruction
CFC1 Move Control Word from Floating Point CTC1 Move Control Word to Floating Point MFC1 Move Word from Floating Point MOV.fmt Floating Point Move
MOVF.fmt Floating Point Move Conditional on Floating Point False MOVN.fmt Floating Point Move Conditional on Not Zero
MOVT.fmt Floating Point Move Conditional on Floating Point True MOVZ.fmt Floating Point Move Conditional on Zero
MTC1 Move Word to Floating Point
Table 3-16 Obsoletea FPU Branch Instructions
a. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture.
Mnemonic Instruction
BC1FL Branch on FP False Likely BC1TL Branch on FP True Likely
Table 3-17 Coprocessor Branch Instructions
Mnemonic Instruction
BC2F Branch on COP2 False
BC2T Branch on COP2 True
Table 3-18 Coprocessor Execute Instructions
Mnemonic Instruction
COP2 Coprocessor Operation to Coprocessor 2
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Table 3-19 Coprocessor Load and Store Instructions
Mnemonic Instruction
LDC2 Load Doubleword to Coprocessor 2 LWC2 Load Word to Coprocessor 2
SDC2 Store Doubleword from Coprocessor 2 SWC2 Store Word from Coprocessor 2
Table 3-20 Coprocessor Move Instructions
Mnemonic Instruction
CFC2 Move Control Word from Coprocessor 2 CTC2 Move Control Word to Coprocessor 2 MFC2 Move Word from Coprocessor 2 MTC2 Move Word to Coprocessor 2
Table 3-21 Obsoletea Coprocessor Branch Instructions
a. Software is strongly encouraged to avoid use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS32 architecture.
Mnemonic Instruction
BC2FL Branch on COP2 False Likely BC2TL Branch on COP2 True Likely
Table 3-22 Privileged Instructions
Mnemonic Instruction
CACHE Perform Cache Operation
ERET Exception Return
MFC0 Move from Coprocessor 0 MTC0 Move to Coprocessor 0 TLBP Probe TLB for Matching Entry TLBR Read Indexed TLB Entry TLBWI Write Indexed TLB Entry TLBWR Write Random TLB Entry
WAIT Enter Standby Mode
3.2 Alphabetical List of Instructions
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Table 3-23 EJTAG Instructions
Mnemonic Instruction
DERET Debug Exception Return SDBBP Software Debug Breakpoint
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ABS.fmt
Format: ABS.S fd, fs MIPS32 (MIPS I)
ABS.D fd, fs MIPS32 (MIPS I)
Purpose:
To compute the absolute value of an FP value Description:fd ← abs(fs)
The absolute value of the value in FPR fs is placed in FPR fd. The operand and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.
This operation is arithmetic; a NaN operand signals invalid operation.
Restrictions:
The fields fs and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE-DICTABLE.
The operand must be a value in format fmt; if it is not, the result is UNPREDICTABLE and the value of the operand FPR becomes UNPREDICTABLE.
Operation:
StoreFPR(fd, fmt, AbsoluteValue(ValueFPR(fs, fmt)))
Exceptions:
Coprocessor Unusable, Reserved Instruction Floating Point Exceptions:
Unimplemented Operation, Invalid Operation
31 26 25 21 20 16 15 11 10 6 5 0
Floating Point Absolute Value ABS.fmt
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ADD
Format: ADD rd, rs, rt MIPS32 (MIPS I)
Purpose:
To add 32-bit integers. If an overflow occurs, then trap.
Description:rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rd.
Restrictions:
ADDU performs the same arithmetic operation but does not trap on overflow.
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL
000000 rs rt rd
0
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ADD.fmt
Format: ADD.S fd, fs, ft MIPS32 (MIPS I)
ADD.D fd, fs, ft MIPS32 (MIPS I)
Purpose:
To add floating point values Description:fd ← fs + ft
The value in FPR ft is added to the value in FPR fs. The result is calculated to infinite precision, rounded by using to the current rounding mode in FCSR, and placed into FPR fd. The operands and result are values in format fmt. Cause bits are ORed into the Flag bits if no exception is taken.
Restrictions:
The fields fs, ft, and fd must specify FPRs valid for operands of type fmt. If they are not valid, the result is UNPRE-DICTABLE.
The operands must be values in format fmt; if they are not, the result is UNPREDICTABLE and the value of the operand FPRs becomes UNPREDICTABLE.
Operation:
StoreFPR (fd, fmt, ValueFPR(fs, fmt) +fmt ValueFPR(ft, fmt))
Exceptions:
Coprocessor Unusable, Reserved Instruction Floating Point Exceptions:
Unimplemented Operation, Invalid Operation, Inexact, Overflow, Underflow
31 26 25 21 20 16 15 11 10 6 5 0
COP1
010001 fmt ft fs fd
ADD 000000
6 5 5 5 5 6
Floating Point Add ADD.fmt
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ADDI
Format: ADDI rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To add a constant to a 32-bit integer. If overflow occurs, then trap.
Description:rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs to produce a 32-bit result.
• If the addition results in 32-bit 2’s complement arithmetic overflow, the destination register is not modified and an Integer Overflow exception occurs.
• If the addition does not overflow, the 32-bit result is placed into GPR rt.
Restrictions:
None Operation:
temp ← (GPR[rs]31||GPR[rs]31..0) + sign_extend(immediate) if temp32 ≠ temp31 then
SignalException(IntegerOverflow) else
GPR[rt] ← temp endif
Exceptions:
Integer Overflow Programming Notes:
ADDIU performs the same arithmetic operation but does not trap on overflow.
31 26 25 21 20 16 15 0
ADDI
001000 rs rt immediate
6 5 5 16
Add Immediate Word ADDI
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ADDIU
Format: ADDIU rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To add a constant to a 32-bit integer Description:rt ← rs + immediate
The 16-bit signed immediate is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rt.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None Operation:
temp ← GPR[rs] + sign_extend(immediate) GPR[rt]← temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith-metic environments that ignore overflow, such as C language aritharith-metic.
31 26 25 21 20 16 15 0
ADDIU
001001 rs rt immediate
6 5 5 16
Add Immediate Unsigned Word ADDIU
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ADDU
Format: ADDU rd, rs, rt MIPS32 (MIPS I)
Purpose:
To add 32-bit integers
Description:rd ← rs + rt
The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rd.
No Integer Overflow exception occurs under any circumstances.
Restrictions:
None Operation:
temp ← GPR[rs] + GPR[rt]
GPR[rd] ← temp
Exceptions:
None
Programming Notes:
The term “unsigned” in the instruction name is a misnomer; this operation is 32-bit modulo arithmetic that does not trap on overflow. This instruction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arith-metic environments that ignore overflow, such as C language aritharith-metic.
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL
000000 rs rt rd
0 00000
ADDU 100001
6 5 5 5 5 6
Add Unsigned Word ADDU
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AND
Format: AND rd, rs, rt MIPS32 (MIPS I)
Purpose:
To do a bitwise logical AND Description:rd ← rs AND rt
The contents of GPR rs are combined with the contents of GPR rt in a bitwise logical AND operation. The result is placed into GPR rd.
Restrictions:
None Operation:
GPR[rd] ← GPR[rs] and GPR[rt]
Exceptions:
None
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL
000000 rs rt rd
0 00000
AND 100100
6 5 5 5 5 6
And AND
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ANDI
Format: ANDI rt, rs, immediate MIPS32 (MIPS I)
Purpose:
To do a bitwise logical AND with a constant Description:rt ← rs AND immediate
The 16-bit immediate is zero-extended to the left and combined with the contents of GPR rs in a bitwise logical AND operation. The result is placed into GPR rt.
Restrictions:
None Operation:
GPR[rt] ← GPR[rs] and zero_extend(immediate)
Exceptions:
None
31 26 25 21 20 16 15 0
ANDI
001100 rs rt immediate
6 5 5 16
And Immediate ANDI
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B
Format: B offset Assembly Idiom
Purpose:
To do an unconditional branch Description:branch
B offset is the assembly idiom used to denote an unconditional branch. The actual instruction is interpreted by the hardware as BEQ r0, r0, offset.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
Operation:
I: target_offset ← sign_extend(offset || 02) I+1: PC ← PC + target_offset
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is±128 Kbytes. Use jump (J) or jump register (JR) instructions to branch to addresses outside this range.
31 26 25 21 20 16 15 0
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BAL
Format: BAL rs, offset Assembly Idiom
Purpose:
To do an unconditional PC-relative procedure call Description:procedure_call
BAL offset is the assembly idiom used to denote an unconditional branch. The actual instruction is iterpreted by the hardware as BGEZAL r0, offset.
Place the return address link in GPR 31. The return link is the address of the second instruction following the branch, where execution continues after a procedure call.
An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address.
Restrictions:
Processor operation is UNPREDICTABLE if a branch, jump, ERET, DERET, or WAIT instruction is placed in the delay slot of a branch or jump.
GPR 31 must not be used for the source register rs, because such an instruction does not have the same effect when reexecuted. The result of executing such an instruction is UNPREDICTABLE. This restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot.
Operation:
I: target_offset ← sign_extend(offset || 02) GPR[31] ← PC + 8
I+1: PC ← PC + target_offset
Exceptions:
None
Programming Notes:
With the 18-bit signed instruction offset, the conditional branch range is±128 KBytes. Use jump and link (JAL) or jump and link register (JALR) instructions for procedure calls to addresses outside this range.
31 26 25 21 20 16 15 0
Branch and Link BAL
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BC1F
Format: BC1F offset (cc = 0 implied) MIPS32 (MIPS I)
BC1F cc, offset MIPS32 (MIPS IV)
Purpose:
To test an FP condition code and do a PC-relative conditional branch Description:if cc = 0 then branch
To test an FP condition code and do a PC-relative conditional branch Description:if cc = 0 then branch