Control Circuit

Control circuit contains 3 parts which are multiplication factor controller, feedback switching detector and glitch-free lock detector. Let us start at multiplication factor controller.

3.2.1 Multiplication Factor Controller

This block certainly controls the enable signal of edge combiner and feedback signal. Circuit input and output pattern is shown in Table 3.1. The relationship between enable signals will be described précised in section 3.7. Through the table and K-map we can know that:

1

And the enable signal of feedback signal is easier to generate form

S

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In this way, we can use the simplest logic gates to generate these control signals.

Table 3.1 Enable signal pattern

Input Output

3.2.2 Feedback switching detector

This block is design to avoid undesired glitch generates when feedback signal is switching. Detector through sensing rising edge and falling edge of signals to judges CP needs to be in charge or discharge condition. In order to sensing rising/falling edge we need rising edge trigger and falling edge trigger. These two blocks is shown in Fig. 3.2 and Fig. 3.3.When input signal has rising/falling edge, output generates a short pulse from 0 to 1. Use these two blocks and D-flip-flop we can acquire feedback switching detector which is shown in Fig. 3.4.

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Fig3.2 Rising edge trigger

Fig. 3.3 Falling edge trigger

Fig. 3.4 Feedback switching detector

By detecting signal rising/falling edge we can judge delay time of VCDL shall be enlarged or shorted. If delay time should be shortened, set_upper sets to 1 and feeds into glitch-free lock detector. Then glitch-free lock detector forces CP charges LF and makes delay time smaller. Set_upper will be cleared at next rising edge of reference clock. Similarly, set_lower will be set for a while when delay time need to be enlarged. Through Fig. 3.5 we can understand how this block work easily. When enable signal falling means feedback signal is changing from VCDL’s 5^th stage to other stage. No matter what stage is chosen to be feedback signal, delay time for each delay cell must be shortened. That is the control voltage must rise at that time, so

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the set_upper signal sets to 1 to force CP charges LF. Similarly, at rising edge of , delay time for each delay cell must be enlarged. So set_lower is set to 1. At reference signal’s rising edge both set_upper and set_lower will be cleared. Based on this movement we can ignore undesired glitch problem.

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Fig. 3.5 Feedback switching detector working example

3.2.3 Glitch-Free Lock Detector

Lock detector is used to generate PFD’s control signals. By using VCDL’s certain stages sample reference clock, lock detector can identify system locking status into 3 states. When upper sets to 1 means VCDL’s delay time is too long in comparison with reference clock’s time period. At the same time, PFD set UP signal to force CP charges so delay time will be shortened. On the contrary, lower sets to 1 means VCDL’s delay time is too short and PFD has to set DOWN signal. When VCDL’s delay time is closed to reference clock’s time period then active is set to 1.

The UP/DOWN signals is determined by PFD at this state. There is only one of Upper, Lower and Active can be 1 at the same time. We can enlarge locking range through separate locking status into Upper, Active and Lower.

In [8], we can see the original type of lock controller and it’s shown in Fig 3.6.

The output signals upper, active and lower are determined by the relationship between reference clock and Bi signals. Where Bi signals represents the i^th stage of VCDL.

Using Bi signals to sample reference clock we can know the lock status. To explain more detailed, I use an example which feedback stage is 8^th stage of VCDL. Lock detector uses 2^nd, 4^th and 6^th stage of VCDL as D-flip-flops’ clock. And D-flip-flops’

inputs are reference clock. Let us see Fig. 3.7. If B2 signal samples at 0 which means the phase difference between reference clock and 2^nd stage of VCDL is π ~ 2π and 8^th stage is 4π ~ 8π. But the phase difference between feedback stage and reference clock should be 2π when system is locked. So at this moment delay should be shortened and output signal should set to 1. Similarly, in Fig. 3.8 we can see that when B2, B4 and B6 sample value are 1, 0 and 1 the phase difference should be 0.67π ~ π, 1.34π ~ 2π and 2π ~ 3π separately. And the phase difference between feedback stage and reference clock is 2.67π ~ 4π still far away from 2π. This locking status is upper too.

In similarly way we can separate locking status into upper, active and lower. There is a summary in table 3.2.

Fig. 3.6 Original type lock controller

Reference Clock B2

B4

B6

B8

Fig. 3.7 Example of lock detector when feedback stage is 8^th stage of VCDL

Fig. 3.8 Example of lock detector when feedback stage is 8^th stage of VCDL

Table 3.2 Lock detector work example when feedback stage is VCDL’s stage 8

Input Phase Difference Locking Status

Q¹ Q² Q³ Stage 2 Stage 4 Stage 6 Stage 8

From Table 3.2 we can get

Actually we can simplify it to

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In this way we can identify locking state into 3 states. In order to cooperates with feedback switching detector we need to make some changes. The structure after modified is shown in Fig. 3.9. The difference from original type is adding two input signals set_upper and set_lower. And we have to clear active and lower to 0 when set_upper is 1. Sets lower and clear active when set_lower is 1. After adding these two signal we can modified the formula to

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Fig. 3.9 Modified lock controller

When feedback stage changes to other stage, the clock of D-flip-flop may be changed. Clock inputs change to 2^nd, 3^rd and 4^th stage when feedback stage is 5^th and 6^th stage. The clock input doesn’t change from feedback stage 8^th to 7^th. The operation