Re-convergence Handling

The number of transient faults are doubled if there is a reconvergent structure along propagation path in the circuit, resulting in the complexity of the SSER analysis increases exponentially. As shown in Figure 4.3, a particle hits the output of G0 and induces a transient pulse. Then, the transient faults propagate along the paths in a block-based way and finally reconverge at the inputs of U0 and U1. Consequently, two positive transient faults appear on the output of U0, and two transient faults with different directions appear on the output of U1.

Particle hit

G0

U0

U1

Figure 4.3: Reconvergent Structure

To resolve this reconvergence problem, we propose a two-stage approach. At the first stage, these transient faults are classified into two groups according to their orientations.

Then the outcomes of the pulse width and the logic probability of these convoluted transient faults are derived at the second stage. In the second stage, the pulse-width distribution of convoluted transient faults is derived by two newly defined merge operations and the logic probability is updated as the union of the ones associated with these transient faults.

4.4.1 Derive Width of Re-Convergent transient faults

The motivation to define new merge operations for two timing signals is that the pulse-width result of transient faults will be underestimated if we adopt traditional one (max) to deduce the result of these convoluted timing signals and the reason is discussed later.

The idea for merging multiple positive transient faults can be defined as:

merge(pw₁, pw₂, · · · , pw_n) =

merge(tf 1, · · · , tf n) + merge(tr1, · · · , trn) (4.6) The merge operation with multiple (>2) operands like Equation (4.6) is computed by taking the 2-operand merge iteratively. Let t⁰ = merge(t₁, t₂), t₁ and t₂ follow normal distribution, and the result t⁰does, too.

merge(t₁, · · · , t_k) = merge(merge(t₁, t₂), · · · , merge(t_k, t_k+1))

= merge(t_1,bk 2c, t_dk

2e,k)

= t1,k (4.7)

The 2-operand merge can be further classified into two types to deduce convoluted pulses with the same orientations and with opposite directions.

To derive the pulse width of reconvergent transient faults with the same orientation, we define the same-orientation merge operation as a worst-case operation that the new pulse is composed of the latest transition signal and the earliest transition signal among these reconvergent transient faults. Take Figure 4.4(a) for example. We denote the later transient fault and earlier transient fault as P1 and P2, respectively. The result of same-orientation mergeoperation performed on P₁and P₂ should be the latest transition and the earliest transition among them, respectively denoted as tr1 and tf 2. However, the result derived by traditional max operation will be tr2 and tf 2, leading to an underestimation for the pulse-width result of the reconvergent transient faults. Same conclusion is also obtained in Figure 4.4(b).

Before performing same-orientation merge operation over two reconvergent transient faults, the existence of overlapping should be checked. As shown in figure 4.4(a), if over-lapping happens, the earliest edge and the latest edge will be chosen to form the a pulse;

otherwise, the width of the new transient fault is the sum of the two convoluted transient faults, as displayed in figure 4.4(b).

On the other hand, for the reconvergent transient faults with opposite orientations, the result of pulse width is determined by the interactive behavior of them. Take Figure 4.5

particle hit

Figure 4.4: Illustration of same orientation merge operation

for example. if the positive transient fault appearing at one input of a AND gate does not overlap the negative transient fault appearing at the other input of the AND gate, the pulse-width result is just the pulse-width of the positive transient fault pw since the negative transient fault is forbidden by the controlling value on the side-input. If the overlapping occurs, the result is computed as the width of positive transient fault pw minus the overlapping part among positive and negative transient faults d due to the negative transient fault masks the part of positive transient fault. Other gate types can be derived similarly.

It is worthy to notice that due to the timing informations of transition signals are pre-served, the issue of reconvergence can be analyzed in such way which is unavailable for in traditional SSER methods [23] [14].

(c) (d)

Figure 4.5: Opposite orientation merge operation at a AND/OR gate

4.4.2 Update Logic Probability

The logic probability at reconvergence fanout nodes should be updated to reflect the reconvergence phenomenon. For convoluted transient faults, the result of logic probability is the union of the ones of these transient faults since this condition is equivalent to that all these transient faults can pass through the reconvergent node. The same result is obtained for the transient faults with the opposite orientation.

Chapter 5

Experimental Results

We implement the proposed framework in C/C++ and exercise on a Linux machine with Intel(R) Core(TM) i7 processor and 16G RAM. To extract the delay characteristics of each gate type, we perform Monte-Carlo SPICE simulation on 4 small benchmark circuits from [23] with a 45nm Nandgate Open Cell Library [36] as the 45 nm cell library.

The method for training these delay data of each gate type can be summarized in three steps: in step 1, all the gates along the propagation path are randomly selected after the path is generated; in step 2, the number of loadings composed of randomly selected gates is arbitrarily chosen for each gate on the propagation path; and in the final step, the charac-teristics of the transient faults induced by radiation particles with various charge strength are extracted by performing Monte-Carlo SPICE simulation. After obtaining these sim-ulation results, we group them according to the charge strength of radiation particle, the transition slope, and the output loadings.

Model errors of a AND gate and a OR gate are summarized in Figure 5.1 and Figure 5.2, respectively, and the average model errors of each gate type are shown in Table 5.1.

All the results of overall SSER of circuits are built on ISCAS85 benchmarks and a series of multipliers. Considering the extremely long runtime of Monte Carlo SPICE simulation (w / 100 runs), we can only afford to perform tests on small circuits with the largest one containing 26 gates, 31 striking nodes and 5 inputs.