Triax 320 Spectrometer
4.4 Current-Voltage and Capacitance-Voltage Curve
In addition to the optical characteristics of the Si nanopillar, the characterizations on its electrical properties are also important to realize the application of the Si nanopillar emitters in IC industry. Because the Si substrate is p-type, the Ni nanodots can be treated as n-type contact similar with the MOS structure during the I-V measurement.
The resistance of Si wafer is decreasing from 41.6 kΩ to 1.92 kΩ after depositing SiO2
and Ni films. As the Ni self-aggregates during thermal annealing, the resistance is increased from 1.92 kΩ to 4.8 kΩ. Moreover, the resistance further increases from 4.8 kΩ to 11.8 kΩ after etching formation of the Si nanopillars. After removing the Ni and SiO2 covering layers, the resistance increases again from 11.8 kΩ to 22.6 kΩ.
1E-4 1E-3 0.01
0 10 20 30 40 50 60 70 80
Si wafer Ni coating Ni self-assembly
Ni nanodot coated Si nanopillars Pure Si nanopillars
Voltage (v)
Log( I )
Fig. 4.8 The comparing I-V curves of different Si structures includes bulk、Ni layer on Si、Ni dots on Si、Si nanopillars with Ni caps、pure Si nanopillars.
Structures Bulk Before RTA After RTA Pillars with Ni Pure pillars Resister (Ω) 41.6 K 1.92 K 4.8 K 11.8 K 22.6 K
Table. 4.1 The resister values of the different Si structures are listed.
(c) (A) (B)
Fig 4.9 (A) The capacitance under different gate voltage. (B) Energy band diagrams and charge distributions of an ideal MOS diode in (B)-(a) accumulation, (B)-(b) depletion, and (B)-(c) inversion.
Another important electrical property is the capacitance-voltage characteristic that stands for the ability of catching electrical charges and the curves are shown in Fig 4.9 -A. According to the Sze’ Semiconductor Devices in p.172, pp=nie(Ei-E
F)/kT, the upward bending of the energy band at the semiconductor surface causes an increase in the energy Ei-Ef, (VG < 0) which in turn gives rise to an enhanced concentration, an accumulation of holes near the oxide-semiconductor interface. This is called the accumulation case shown in Fig 4.9-B-a. When a small positive voltage (VG > 0) is applied to an ideal MOS diode, the energy bands near the semiconductor surface are bent downward, and the majority carriers (holes) are depleted. This is called the depletion case shown in Fig 4.9-B-b. When a larger positive voltage is applied, the energy bands bend even more so that the intrinsic level Ei at the surface crosses over the Fermi level as shown in Fig 4.9-B-c. That means the positive gate voltage starts to induce excess negative carriers at the SiO2-Si interface. The electron concentration in
the semiconductor is given by np=nie(EF-E
i)/kT. Because the electrons (minority carriers) at the surface is greater than holes (majority carriers), the surface is inverted that is called inversion case. However, the simple criterion for the onset of strong inversion is that the electron concentration at the surface is equal to the substrate impurity concentration, i.e. ns=NA (Ei=EF). Since NA=nieqφB/kT ,(φB is the energy difference between EF and Ei), the surface potential φS(inv)≒2φB=2kT*(ln(NA/ni))/q. In the other extreme, when strong inversion occurs, the width of the depletion region will not increase with a further increase in applied voltage. This condition takes place at a metal-plate voltage that causes the surface potential φB to reach φs (inv). At the onset of strong inversion, the voltage is called threshold voltage VT = (qNAWm/C0) + φs (inv) = (((2qεsNA (2φB) ) 1/2 /C0))+2φB. For p-type Si substrate, VT is positive because the bias voltage of the Si substrate must be on the negative region to get electrons for inversion. On the contrary, VT is negative for n-type Si substrate.
(a) (b)
(A) (B)
Fig 4.10 Effect of a sheet charge within the oxide. (A)-(a) Condition for VG = 0. (A)-(b) Flat-band condition. Effect of a oxide charge and interface traps on the C-V characteristics of an MOS diode.
XO
However, consider a positive sheet charge Q0 within the oxide and this charge will induce negative charges partly in the metal and partly in the semiconductor as shown in Fig. 4.10-A-a. To reach the flat-band condition (i.e. no charges induced in the semiconductor), we must apply a negative voltage to the metal, as shown in Fig.
4.10-A-b Until the electric field at the semiconductor surface is zero, the flat-band voltage VFB = -ε0 X0 = -Q0X0/εox = -Q0X0/C0d. Due to Q0, the c-v curve will be parallel-shifted that is illustrated from the c-v curve (a) to (c) in Fig. 4.10-B. In this condition, the threshold voltage VT = VFB + (((2qεsNA (2φB)) 1/2 /C0)) + 2φB.
Fig 4.11 The C-V curves are measured from Si bulk and Si nanopillar array .
In this essay, we measured the c-v curves of bulk and pillar MOS (metal-oxygen-semiconductor) structures shown in Fig.4.11. The scanning rate is 1 s/point and the step point is 0.5 V/point in the c-v measurement. The apparent c-v curve shift from the bulk MOS diode to the nanopillar MOS diode is about 60 V that is surely caused by the positive defect charges resulting in the variation of VT base on the MOS capacitance rule in Sze’s Semiconductor Devices. The positive-charged defects might
-60 -40 -20 0 20 40 60 80
be activated during RTA and etching process. According to E. H. Poindexter in 1988, the charge hysterest in the Si nanopillar is mainly produced by the netraul oxygen vacancy (NOV) because NOV defect will catch positve charge and become positive charges. The reactive equation O3≡Si-Si≡O3 + hole→O3≡Si˙+Si≡O3 and this kind of defects is almost induced at the high temperature annealing.[4.22] As the rule C = εA / Xox, the capacitance should decrese in the small area. Howeever, the accumulation region, the Cox of the MOS diode made on Si-nanopillar roughened substrate is about 35 pF which is slightly larger than that made on the Si substrate deposited with 200-Å SiO2 and 50-Å Ni film 27.5 pF. This is caused by the current leakage resulted from the bad insulating quality of SiO2 film. However, the current leakage can be deduced by the nanopillar form possibly because of the air-filled area in the structure. And due to the oxidation of the Si nanopillars, this stores more electric charges and thus increases the capacitance. In the inversion region, the CG of the MOS diode made on Si-nanopillar roughened substrate is about 3 pF which is slightly smaller than that made on the Si substrate deposited with 200-Å SiO2 and 50-Å Ni film 10 pF. From the Fig 4.9(B)-(c), the CG = Cox Cs/ (Cox + Cs). According to the above description that the Cox of the MOS diode made on Si-nanopillars is slightly larger than that made on the Si substrate deposited with 200-Å SiO2 and 50-Å Ni film, the CG of Si pillar MOS diode should be larger than the Si bulk MOS diode. Nevertheless, the small area decrease the Cs largely and in trade-off condition CG decreases finally. Besides, the switching time of pillar MOS diode of 1mins is smaller than the bulk MOS diode of 2 mins. Owing to this advantage, the Si-nanopillar structure has been used in many transistor devices such as MOSFETs (metal-oxide-semiconductor field effect transistor) [4.23] and SGTs (surrounding gate transistors) [4.10] due to its low threshold voltage and low parasitic capacitance. Comparing with the bulk Si structure, the Si nanopillars owned the high-speed charging and discharging features but posses the problem of relatively large
leakage current.
4.5 Conclusions
The Si nanopillars with diameter 30-70nm presents a strong and broad PL spectrum where the peaks at 415-455 nm with linewidths of 35-50 nm were originated from the transitions of the weak oxygen bond, and the NOV defects. The saturating peak of 450 nm under high pumping power density 300 W/cm2 is due to the finite luminescent centers in this defect. These two defects are mainly produced from the RTA (thermal activation) and etching process (O2 ionized). The μ-PL at wavelength of 750 nm appeared under a pumping density that is 104 times larger than that used in the common PL system. A blue-shift from 759 nm to 754 nm in μ-PL after the oxidizing period from 1 day to 10 days and this peak saturating under larger pumping power density has proved the existence of quantum confined phenomenon in Si nanopillars. The long-term oxidization (up to 10 days) of Si nanopillars degrades the Si quantum confining centers and increases the luminescent centers of the oxygen defects in opposite. In the aspect of reflectance, the Si-nanopillars exhibit a smaller reflectance than the Si substrate because of the highly roughened surface. In electrics, pillar MOS diode owns a lower resistance of 11.8 kΩ than bulk MOS diode 1.92 KΩ because of the current leakage proven by the c-v analysis. Finally, comparing the bulk and pillar MOS diode, there are some good performances for the pillar MOS diode including lower threshold voltage VT 、high charging and discharging speed、higher Cmax and lower Cmin. After analyzing the flat-band voltage VFB, the VT shift from bulk MOS diode and pillar MOS diode is about -60 V mainly due to the positive charge defects (NOV defects：O3≡Si-Si≡O3 + hole→O3≡Si˙+Si≡O3) which were originating in the SiO2
during RTA process. Moreover, the charge hysteresis of pillar MOS diode c-v curve
is also affected by the NOV defects. [4.22] Because the current leakage can be deduced by pillar structure, Cox of pillar MOS diode 35 pF is larger than bulk MOS diode 27.5 pF. However, the smaller surface area of pillar MOS diode decrease the surface capacitance Cs resulted in the smaller Cmin 3 pF than bulk MOS diode 10pF.
4.6 References
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[4.2] A. G. Nassiopoulos, S. Grigorpoulos, D. Papadimitriou, and E. Gogolies, Appl.Phys. Lett. 66, 1114 (1995).
[4.3] S. Grigorpoulos, E. Gogolies,A. D. Tserepi, and A. G. Nassiopoulos, J. Vac. Sci.
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[4.4] J. Westwater, D. P. Gossian, S. Tomiya,Y. Hirano, and S. Usui, Mater. Res. Bull.
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[4.6] N. T. Bagraev, E. I. Chaikina, L. E. Klyachkin, I. I. Markov, and W. Gehlhoff, Superlattic. & Microstruture 23, 337 (1998).
[4.7] S. Horiguchi, Superlattice & Microstructure 23, 355 (1998).
[4.8] Y. Zheng, C. Rivas, R. Lake, and T. B. Boykin, IEEE Trans. on Electron Devices. 52, 1097 (2005).
[4.9] A. V. Karabutov, V. D. Frolov, A. V. Smakin, and G. A. Shafeev, IEEE Proceedings of the 14th International Vacuum Microelectronics Conference (IVMC2001) pp.115 (2001).
[4.10] M. Terauchi, N. Shigyo, A. Nitayama and F. Horiguchi, IEEE Trans. on Electron Devices 44, 2303 (1997).
[4.11] V. V. Poborchii, T. Tada and T. Kanayama, Optics Communication 210, 285 (2002).
[4.12] A. G. Drzazga, j. Dziuban, W. Drzazga, A. Kraj and J. Silberring, Technical Digest of the 17th International Vacuum Nanoelectronics Conference (IEEE Cat.
No.04TH8737). IEEE. pp.290 (2004).
[4.13] D. Papadimitriou and A.G. Nassiopoulou, J. Appl. Phys. 84, 1059 (1998).
[4.14] S. I. Yanagiya, M. Matsui, M. Yoshimoto, T. Ohnishi, K. Yoshida, K. Sasaki and H. Koinuma, Appl. Phys. Lett. 71, 1409 (1997).
[4.15] A. G. Nassiopoulos, S. Grigoropoulos and D. Papadimitriou, Appl. Phys. Lett.
69, 2267 (1996).
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Grilli, and M. Guzzi, Appl. Phys. Lett. 66, 851 (1995).
[4.17] R. Tohmon, Y. Shimogaichi, H. Mizuno, Y. Ohki, K. Nagasawa, and Y. Hama, Phys. Rev. Lett. 62, 1388, (1989).
[4.18] H. Nishikawa, R. E. Stahlbush, and J. H. Stathis, Phys. Rev. B 60, 15910 (1999).
[4.19] L. Skuja, J. Non-Cryst. Solids 239, 16 (1998).
[4.20] J. Q. Xi, J. K. Kim and E. F. Schubert, Nano lett. 5, 1385 (2005) [4.21] J. Springer, et al. J. Appl. Phys. 96, 5329 (2004)
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Chapter 5 Summary 5.1 Summary
By using a highly heat-accumulated and less-adhesive SiO2 buffered layer, we successfully demonstrated a rapid self-assembly method for aggregating Ni nanodots on Si substrate as the etching mask. Due to the highly heat dissipated feature of Si substrate with a thermal conductivity of 148 W/m-K, the 200Å thin SiO2 layer with the ultralow thermal conductivity of only 1.35 W/m-K facilitates the self-assembly of Ni nanodots from retaining the thermal power on the SiO2 layer. The required annealing time for synthesizing the Ni nanodots with comparable density and size is greatly shortened to <30 seconds. The self-aggregated Ni nanodots with highest density and smallest size of 7.2×1010 cm-2 and 33 nm, respectively, are obtained at the optimized RTA condition at 850oC for 22 sec. The larger size and smaller density of Ni nanodots could be obtained after RTA if the SiO2 film or the Ni layer becomes thicker.
Raising the RTA temperature 、lengthening the RTA time and depositing thick SiO2
film or Ni layer will concurrently cause the effects of size enlargement and density dilution.
Si nanopillars with the high aspect ratio were formed on Si substrate with the self-assembled Ni nanodots annealing at 850oC for 120 sec by ICP-RIE. Limited to the size and the density of the Ni nanodots, the average diameter of the density Si nanopillars are nearly 50 nm and 1010 cm-2. Comparing to the results of the Korean [5.1], the density of the Si nanopillars in our experiment is over ten times larger than the Korean because of the Ni nandot mask of the high density. The etching depth was proportion to the magnitude of CF4 flowing 、 Ar flowing 、 the chamber pressure、the etching time、the bias power and the rf power, but the etching
selectivity between the Si and Ni dots is completely opposite. Because of the tradeoff of the etching depth and the etching selectivity, there is an optimum value to every etching parameter. In our experiment, the optimum aspect ratio of Si nanopillars happened with the average diameter and depth of 50 nm and 400 nm in our experiment when the gas flowing of CF4 and Ar、the bias/rf power、the chamber pressure、the etching time were set at 40sccm、40sccm、50(W)/150(W)、0.66pa and 7 min.
The Si nanopillar sample presents a strong and broad PL spectrum where the peaks at 415-455 nm with linewidths of 35-50 nm were originated from the weak oxygen bond, and the peak at 455 nm was attributed to the transition between the ground state (singlet) and the elevated state (triplet) of the NOV defects. The changeless peak and the defect peak saturating in the dependent-power PL were because the density of the pumped energy level saturated under the high pumping power. This is also a proof that the two peaks are from the defects not from the Si quantum confine. The peak wavelength of 750nm appeared in the μ-PL pumped by the 104 times larger power density than the PL that could pump more emitting centers in the Si nanopillars. The quantum effect was proven by the 750 nm peak shifting from 759 nm to 754 nm after the oxidation and saturating under the larger pumping power density. The oxidizing of Si nanopillars decreased the Si quantum confining centers and it also increased the luminescent centers of the oxygen defects. The reflectance of the pure Si nanopillars was smaller than the Si bulk because of the highly rough surface. Otherwise, the Si nanopillar structure owns a low resister 22 KΩ and a good protection against the current leakage comparing to the Si bulk structure.
According to the special characteristics in electrics and in optics, the Si nanopillars can be used extensively as sensors、field emitter to pump phosphors、highly dense memory and solar cells.