Cycling Dependence - Program Disturb Behavior

Chapter 3 Program Disturb Induced Erase State V t Shift

3.4 Program Disturb Behavior

3.4.3 Cycling Dependence

In a P/E stressed cell, the Vt shift induced by program disturb is found to be larger than that in a fresh cell. Fig.3.8 shows the threshold voltage shift versus P/E cycle number. The dependence of the Vt shift implies that the charge gain behavior in low Vt state is due to positive oxide charge detrapping. At low P/E stress, oxide trap creation is minimal and thus Vt shift is small.

3.4.5 Summary

Based on this work, we realize that erase state Vt drift measured by Agilent 4155C is underestimated since charge tunneling starts immediately after erase. From the above measurement results, micro-second time scale Vt shift can be probed. The Vt shift is much more severe in an array because of accumulated gate stress time during programming.

3.5 Modified Erase Scheme

Except for room-temperature drift and read disturb, our study showed that program disturb is also a reliability concern in the low Vt state. Some ways to prevent disturb such as isolated sector structure was proposed [36]. An alternative approach is

to use an appropriate voltage pulse to reduce this stress effect. After BTBT hot hole erase, an extra electrical anneal is reported to be effective [34]. As positive charges are accumulated during erase, subsequent anneal step will remove the cycling induced positive charges in the bottom oxide. An electrical pulse at Vg=10V and Vd=4V can significantly reduce program disturb effect (Fig. 3.9).

^0.3

Vg=5V (read.-disturb)

Fig. 3.7 V^t shift versus wait time after erase.

11V 20ms

∆ Vt (Volts)

Wait time (sec)

1 0

0 . 0 0

0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 0

11V 20ms

∆ Vt (Volts)

Wait time (sec)

Fig. 3.8 Cycle number dependence of Vtshift. Note that no V^t shift observed in a fresh cell. After 10K P/E cycles, there is a 0.17V Vt shift after 100ms disturb.

0 . 0 0 0 . 0 5 0 . 1 0 0 . 1 5 0 . 2 0

2 0 m s 4 0 m s 1 0 0 m s

∆ Vt (Volts)

P/E cycles

Vt shift of conventional erase and modfiied erase with an electrical anneal step. The anneal voltage is Vg/Vd=10/4V.

Chapter 4 P/E Cycling Induced Read Current Noise

4.1 Introduction

In this chapter, we investigate P/E cycling induced random telegraph noise (RTN) in non-uniform charge storage nitride flash cells for the first time. The amplitude of RTN increases with P/E cycle number and with decreasing gate length. Non-uniform charge storage by channel hot electron programming can further enhance read current fluctuation. The large amplitude of read current fluctuation implies we must allow for more margins in cell operation and needs careful attention especially in Multi-level cell (MLC) application.

Therefore, to probe the RTN phenomenon and to find the solutions will be an important issue in SONOS type two-bit storage flash memory cells. According to our investigation, read current noise can be significantly reduced by the improvement of bottom oxide reliability.

4.2 Random Telegraph Noise Measurement

The charge transport through a MOSFET device characterized by discrete switching events of the drain current, has often been observed and attributed to the trapping/detrapping of conduction carriers by a single defect near Si/SiO2 interface [37]-[39]. Different names exist for the phenomenon, like burst noise or Random Telegraph Noise (RTN). Micro-second Transient measurement system we mentioned at chapter 3 for measuring read current noise is shown in Fig. 4.1. This setup can monitor the drain current noise in fixed read bias. The sampling rate in our experiments is 10khz, which enables the observation of fast transitions of read current with time constant down to 0.1ms, which corresponds to 10⁵ reading in each measurement of 10 seconds. The devices used in this work have a gate length of

0.35µm and a gate with from 0.5µm to 0.3µm.

4.3 P/E Cycling Stress

In a P/E cycled cell, the read current fluctuation induced by oxide trap is found to be larger than that in a fresh cell. Fig. 4.2 shows read current fluctuation at program state in a fresh cell, after 1k P/E cycles and after 100k P/E cycles. The cell biased in weak inversion and the read current is near 1µA. Apparent random telegraph noise patterns are observed in a 100k P/E cycled cell while it is undetected in a fresh cell.

The RTN rises from the charging/discharging of single oxide trap or multiple oxide traps created by P/E cycling stress [40]. At a low cycle number the RTN exhibits two-level transitions (Fig. 4.2(b)) while at a large cycle number multi-level transitions (4-level) are occasionally observed (Fig. 4.2(c)). These multi-level transitions, superimposed by several independent two-level RTN waveforms, may exhibit a large

∆Id and result in a read failure.

The dependence of noise amplitude on read current level is shown in Fig. 4.3. In this measurement, a NROM cell is programmed to different Vt and the reverse read bias is at |Vds|=1.5V and Vgs=4V. The cycle number is 100 that only two-level transitions are obtained. As shown in Fig. 4.3(a), ∆Id is found to increase from 0.04µA in a high-Vt cell (1µA read current) to 0.18µA in a low-Vt cell (30µA read current).

4.4 Length Dependence & Non-uniform V

Effect

The gate length effect on RTN is shown in Fig. 4.4. The read current level is about 1µA. The RTN amplitude with two-level transitions is shown in Fig. 4.4(a), a noticeable increases of ∆Id with decreasing gate length [41]. A two-dimensional device simulation is performed to calculate the gate length dependence. A similar trend is obtained (Fig. 4.5). Moreover, RTN is found to be further enhanced by localized charge storage. Fig. 4.6 shows the current fluctuations by FN injection and

R

Experimental setup for RTN measurement.

Fig. 4.1

0.0 0.5 1.0 1.5 2.0

Representative RTN traces in a NROM cell (W/L=0.35µm/0.3µm). (a) fresh, (b) 1k P/E cycles, (c) 100k P/E cycles.

Fig. 4.2

Fig. 4.3 Comparison of RTN amplitude in program-state and in erase-state (b) Dependence of ∆Id (two-level transition) on read current. The P/E cycle number is 100 P/E. The reverse read bias is Vg=4V, Vs=1.5V and Vd=0V.

Fig. 4.4 (a) Comparison of RTN amplitude for Lg=0.3µm and 0.5µm.

(b) Dependence of ∆Id (two-level transition) on gate length.

The read current level is about 1µA.

0.30 0.35 0.40 0.45 0.50 0.00

0.30 0.35 0.40 0.45 0.50

0.00 0.2 0.3 0.4 0.5 0.00

0.03 0.06 0.09 0.12

∆ I d (µ A)

Gate length (µm)

CHE injection FN injection

0.2 0.3 0.4 0.5

0.00 0.03 0.06 0.09 0.12

∆ I d (µ A)

Gate length (µm)

CHE injection FN injection

Fig. 4.5 Calculated gate length dependence of two-level RTN amplitude from 2D device simulation. For CHE injection, the trapped charge width is assumed to be 30nm. FN injection has uniform charge storage. The parameters in simulation are not calibrated.

1.0

Fig. 4.6 Typical RTN traces for uniform FN injection (a) and channel hot electron injection (b). Both cells have the same P/E stress conditions.

CHE injection, respectively. The two cells experience the same cycling procedure but have different injection conditions in the last programming. In the uniform FN injection cell (Fig. 4.6(a)), RTN is very small or undetectable in a measurement span of 4 seconds. The simulated result in Fig 4.5 also shows that uniform injection yields smaller RTN. Our result here is consistent with earlier work in [42] that non-uniform channel Vt-distribution can increase 1/f noise. Fig 4.7 shows the maximum read current fluctuation and corresponding number of levels in read current in a 0.3µm cell.

The read current is about 30µA. At 100k P/E cycles, 5-level transitions in read current is noticed and maximum ∆Id is ~0.7µA in a sampling space of 10⁵ reading.

RTN with more levels and a large ∆Id is still expected as more reading are taken [43].

4.5 Oxide Process Effect

To evaluate bottom oxide process effect on RTN, two different oxide process conditions with a 0.5µm gate length (device A and device B) are used. Device B is known to have better oxide endurance from a charge pumping measurement result (Fig. 4.8(a)) RTN traces in device A and B are shown in Fig. 4.8. Note that device B exhibits smaller amplitude in read current fluctuation. This is because device B has less oxide traps creation and thus the probability of multi-level RTN is much reduced.

(a)

Fig. 4.7 Maximum ∆Id observed at a read current of 30µA from multi-level RTN. The sampling size is 10⁵readings.

0 0 .2 0 .4 0 .6 0 .8

Max. ∆ I d (µ A)

P/E cycles

10 10

10

⁵

L g =0.3µm

0 0 .2 0 .4 0 .6 0 .8

Max. ∆ I d (µ A)

P/E cycles

10 10

10

⁵

L g =0.3µm

Fig. 4.8 (a) The increment of charge pumping current (Icp) in device A and device B after 10k P/E cycles. (b) RTN traces in Device A after 10k P/E cycles (c) RTN traces in Device B after 10k P/E cycles.

Chapter 5 Conclusion

Programmed charge distribution in the ONO layer and the effects of read current noise in a localized trapping storage cell have been discussed in this thesis. The lateral distribution of programmed charge is investigated by using a charge pumping technique. The secondly programmed bit has a broader trapped charge distribution than the first programmed bit. The relationship between trapped charge and P/E cycle stress can be realized.

By using our micro-second transient measurement circuit, word-line disturb induced threshold voltage shift is investigated and is found to be a serious reliability issue in this cell. Oxide charge trapping/detrapping induced read current fluctuation is discussed. Read current noise is increased in localized charge storage cells due to non-uniform Vt distribution. As the cycle number increases, the read current instability caused by RTN will become more severe. The improvement of bottom oxide reliability can significantly reduce this effect.

Reference

[1] Herman E. Maes and Jan F. Van Houdt, “Silicon Scaling and its Consequences for Memory Technology,” Non-Volatile Semi. Memory Workshop, pp. 7-10, 2003.

[2] H. C. Pao and O’Connell, “Memory Behavior of an MNS Capacitor,” Appl.

Phys. Lett., Vol. 12, p. 260, 1968.

[3] H. A. R. Wegener, A. J. Lincoln, H. C. Pao, M. R. O’Connel, and R. E. Oleksiak,

“The Variable Threshold Transistor, A New Electrically-Alterable, Non-destructive Read-only Storage Device”, IEEE IEDM Abstract, p. 420, 1967.

[4] L. A. Kasprzak, R. B. Laibowitz, and M. Ohring, “Dependence of the Si-SiO2 Barrier Height on SiO2 Thickness in MOS Tunnel Structures”, J. Appl. Phys., Vol. 48, p. 4281, 1977.

[5] S. Lai, “Flash Memories: Where we are and where we are going”, IEDM Tech.

Dig., pp. 971-973, 1998.

[6] M. L. French and M. H White, “Scaling of Multidielectric Nonvolatile SONOS Memory Structures”, Solid-State Electronics, Vol. 37, p.1913, 1995.

[7] Y. L. Yang, A. Purwar, and M. H. White, “Reliability Considerations in Scaled SONOS Nonvolatile Memory Devices”, Solid-State Electronics, Vol. 43, p.2025, 1999.

[8] M. H. White, Y. L. Yang, A. Purwar and M. L. French, “A Low Voltage SONOS Nonvolatile Semiconductors Memory Technology”, Non-Volatile Semi. Memory Workshop, p. 52, 1996.

[9] Y. L. Yang and M. H. White, “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures”, Solid-State Electronics, Vol. 44, p.949, 2000.

[10] J. Bu and M. H. White, “Effects of Two-Step High Temperature Deuterium Anneals on SONOS Nonvolatile Memory Devices”, IEEE Elect. Dev. Lett., Vol.

22, p. 17, 2001.

[11] B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A Novel Localized Trapping, 2–Bit Nonvolatile Memory Cell”, IEEE Elect. Dev.

Lett., Vol. 21, pp. 543-545, 2000.

[12] B. Eitan, P. Pavan, and I. Bloom, “NROM^TM – A New Technology for Non-Volatile Memory Products” Solid-State Electronics Vol. 46, pp.

1757-1763, 2002.

[13] B. Eitan, “Non-Volatile Semiconductor Cell Utilizing Asymmetrical Charge Trapping”, U. S. Patent 5 768192, June 16, 1998.

[14] M. K. Cho and D. M. Kim, “High Performance SONOS Memory Cells Free of Drain Turn-On and Over-Erase: Compatibility Issue with Current Flash Technology”, IEEE Elect. Dev. Lett., Vol. 21, p. 399, 2000.

[15] M. White, “On the Go with SONOS,” IEEE Circuit and Device Magazine, pp.22-31, 2000.

[16] W. J. Tsai, N. K. Zous, C. J. Liu, C. C. Liu, C. H. Chen, Tahui Wang, Sam Pan, Chih-Yuan Lu, and S. H. Gu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell” IEDM Tech. Dig., pp. 719-722, 2001.

[17] L. Larcher, G. Verzellesi, P. Pavan, E. Lusky, I. Bloom and B. Eitan, “Impact of Programming Charge Distribution on Threshold Voltage and Subthreshold Slope of NROM Memory Cells,” IEEE Trans. Electron Devices, pp.1939-1946,2002.

[18] Y. Roizin, M. Gutman, E. Aloni, V. Kairys, and P. Zisman, “Retention Characteristics of microFLASH^TM Memory (Activation Energy of Traps in the ONO Stack)”, Non-Volatile Semi. Memory Workshop, pp. 128-129, 2001.

[19] E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, “Electron Discharge Model of Locally-Trapped Charge in Oxide-Nitride-Oxide (ONO) Gate for NROM^TM Non-volatile Semiconductor Memory Devices”, Ext. Abst. Conf.

Solid State Devices and Materials, pp. 534-535, 2001.

[20] W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, Tahui Wang, Sam Pan, and Chih-Yuan Lu, “Cause of Data Retention Loss in s Nitride-Based Localized Trapping Storage Flash Memory Cell”, Proc. Int.

Reliability Phys. Symp., pp. 34-38, 2002.

[21] Tahui Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T C. Lu, Sam Pan, and Chih-Yuan .Lu, “Reliability Models of Data Retention and Read-Disturb in 2-bit Nitride Storage Flash Memory Cells (Invited Paper),”

IEDM Tech. Dig., pp. 169-172, 2003.

[22] M. Jannai, “Data Retention, Endurance and Acceleration Factors of NROM Devices,” Proc. Int. Reliability Phys. Symp., pp. 502-505, 2003.

[23] S. H. Gu, M. T. Wang, C. T. Chan, N. K. Zous, C. C. Yeh, W. J. Tsai, T. C. Lu, Tahui Wang, Joseph Ku, and Chih-Yuan Lu, “Investigation of Programmed Charge Lateral Spread in a Two-bit Nitride Storage Flash Memory Cell by Using a Charge Pumping Technique,” Proc. Int. Reliability Phys. Symp., pp.

639-640, 2004.

[24] W. J. Tsai, N. K. Zous, M. H. Chou, Smile Huang, H. Y. Chen, Y. H. Yeh, M. I.

Liu, C. C. Yeh, Tahui Wang, Sam Pan, and Chih-Yuan Lu, “Cause of Erase Speed Degradation During Two-bit per Cell Operation of A Trapping Nitride Storage Flash Memory Cell,” Proc. Int. Reliability Phys. Symp., pp. 522-526, 2004.

[25] W. Chen and T. P. Ma, “A New Technique for Measuring Lateral Distribution of Oxide Charge and Interface Traps near MOSFET Junctions,” IEEE Elect.

Dev. Lett., Vol. 12, p.393, 1991.

[26] Wenliang Chen, Artur Balansinski and T. P. Ma, “Lateral Profiling of Oxide Charge and Interface Traps near MOSFET Junctions,” IEEE Trans. Electron Devices, Vol. 40, pp.187-196, 1993.

[27] Chun Chen and T. P. Ma, “Direct Lateral Profiling of Hot-Carrier-Induced Oxide Charge and Interface Traps in Thin Gate MOSFET’s,” IEEE Trans.

Electron Devices, Vol. 45, pp.512-520, 1998

[28] Yujun Li and T. P. Ma, “Suppression of Geometric Component of Charge-Pumping Current in SOI/MOSFETs,” Int. Symp. On VLSI-TSA., pp.

144-148, 1995

[29] Tran Ngoc Duyet, Hiroki Ishikuro, Makoto Takamiya, Takuya Saraya and Toshiro Hiramoto, “Effects of Body Reverse Pulse Bias on Geometric Component of Charge Pumping Current in FD SOI MOSFETs,” Proc. IEEE Int. SOI Conf., pp. 79-80, 1998.

[30] MEDICI User’s Manual, Synopsis.

[31] W. J. Tsai, C. C. Yeh, N. K. Zous, C. C. Liu, S. K. Cho, Tahui Wang, S. Pan, and Chih-Yuan Lu, “Positive Oxide Charge-Enhanced Read Disturb in a Localized Trapping Storage Flash Memory Cell,” IEEE Trans. Electron Devices, pp. 434-439, 2004.

[32] F. Schmidlin, “Enhanced Tunneling Through Dielectric Films due to Ionic Defects,” J. Appl. Phys., Vol. 37, pp. 2823-2832, 1966.

[33] Anirban Roy, Reza Kazerounian, Adam Kablanian, and Boaz Eitan, “Substrate Injection Induced Program disturb – A New Reliability Consideration for Flash-EPROM Arrays,” Reliability Phys. Symp. Annual Proc., pp. 68-75, 1992.

[34] C. C. Yeh, W. J. Tsai, T C. Lu, H. Y. Chen, H. C. Lai, N. K. Zous, Y. Y. Liao, G.

D. You, C. C. Liu, F. H. Hsu, L. T. Huang, W. S. Chiang, C. J. Liu, C. F. Cheng, M. H. Chou, C. H. Chen, Tahui Wang, Wenchi Ting, Sam Pan, Joseph Ku, and Chih-Yuan .Lu, “Novel Operation Schemes to Improve Device Reliability in a Localized Trapping Storage SONOS-type Flash Memory Cells,” IEDM Tech.

Dig., pp. 173-176, 2003.

[35] T. Wang, N. K. Zous, J. L. Lai, and C. Huang, “Hot Hole Stress Induced Leakage Current Trancient in Tunnel Oxides,” IEEE Elect. Dev. Lett., Vol.19, pp. 411-413, 1998.

[36] Paolo Cappelletti, Carla Golla, Piero Olivo, and Enrico Zanoni, Flash Meomories, Kluwer Academic Publishers, 1999

[37] K. K. Hung, P. K. Ko, Chenming Hu, and Yiu Chung Cheng, “Random Telegraph Noise of Deep-Submicrometer MOSFET’s,” IEEE Elect. Dev. Lett., Vol. 11, pp.90-92, 1990.

[38] P. Fang, Kwok K. Hung, Ping K. Ko, and Chenming Hu,

“Hot-Electron-Induced Traps Studied Through the Random Telegraph Noise,”

IEEE Elect. Dev. Lett., Vol. 12, pp.273-275, 1991.

[39] Ming-Horn Tsai, Hirotaka Muto, and T. P. Ma, “Random Telegraph Signals Arising from Fast Interface States in Metal-SiO2-Si Transistors,” Appl. Phys.

Lett., Vol. 10, pp. 1691-1693, 2001.

[40] Ming-Horn Tsai, T. P. Ma, “The Impact of Device Scaling on the Current Fluctuation in MOSFET’s,” IEEE Trans. Electron Devices, Vol. 41, pp.2061-2068, 1994.

[41] Ming-Horn Tsai, T. P. Ma, and Terence B. Hook, “Channel Length Dependence of Random Telegraph Signal in Sub-Micron MOSFET’s,” IEEE Elect. Dev. Lett., Vol. 15, pp.504-506, 1994.

[42] Jun-Wei Wu, J. C. Kuo, Kai-Lin Chiu, Chih-Chang Cheng, W. Y. Lien, G. W.

Huang, and Tahui Wang, “Modeling of Pocket Implant Effect on Drain Current Flicker Noise in High Performance Analog CMOS Devices,” Ext. Abst. Conf.

Solid State Devices and Materials, pp. 416-417, 2003.

[43] Akiko Ohata, Akira Toriumi, Masao Iwase, and Kenji Natori, “Observation of Random Telegraph Signals: Anomalous Nature of Defects at the Si/SiO2

Interface,” J. Appl. Phys., Vol. 6, pp. 200-204, 1990.