Sample-and-hold
4.2 D ESIGN OF D IGITAL V OLTAGE C ONTROLLER
4.2.1 Design of Voltage Compensator
For designing the digital control compensator, the effect of the output voltage ripple on inductor current command should be concerned at first. Fig. 4.7 shows that the output voltage ripple will be introduced into the output of voltage compensator (Vcomp). This ripple induced harmonic components in the inductor current command (Vmultout) [21].
Vmultin
Vcomp Vcomp,avg
Vmultout
Vin,pk
×
KiΔvcomp Vmultin
Vcomp Vcomp,avg
Vmultout
Vin,pk
×
KiΔvcomp
Fig. 4.7. The effect of output voltage ripple on inductor current command.
The feedback of rectified line voltage and the output of the voltage compensator can be represented as follows
(4-25)
The output of multiplier (Vmultout) will equal to the product of Vmultin and Vcomp can be given
The relationship between the normalized output voltage ripple of voltage compensator and the THD of the inductor current command is an important issue.
2
The fundamental component of the inductor current command can be noticed by Fourier series.
[ ]
And so on, the THD of the inductor current command can be got.
avg
If given a maximum acceptable THD of 10 % at the rated output power, (4-27) means that the normalized inductor current command ripple should be smaller than 10 %.
Selecting the voltage compensator gain at 120 Hz should be based on this criterion.
The design of the digital voltage compensator of CRM PFC controller significantly influences the performance of the circuit in terms of the THD of the line current.
Although lower bandwidth can effectively eliminate the influence of output voltage ripple on current command, it will also reduce the dynamic response. The proper bandwidth is concerned. For eliminating the steady-state error and regulating bandwidth, the proportional-integral (PI) controller is selected in this thesis. The voltage loop with digital voltage compensator is shown in Fig. 4.8.
Vref + Vout
Fig. 4.8. The block diagram of digital voltage control loop.
The following equations are derived in Fig. 4.8.
) 1 for reference voltage of ADC of output voltage feedback, BDAC = 10 for bit resolution of DAC, Vref,DAC = 3.3 V for reference voltage of DAC, and H = 0.00625 for feedback gain of output voltage.
For the requirement given in section 4.2.3.1, the distortion requirement of current command is obtained
2 . avg out
comp
Furthermore, the ripple of voltage compensator output can be represented as .
From chapter 2, the output voltage ripple can be known.
, .
dc line out ripple out
dc C V
V P
⋅
= ⋅
Δ ω (4-35)
Following (4-33), the gain of the digital voltage compensator at 2ωline should satisfy
.
C line sample
η
ω
(4-36)
The voltage open loop transfer function is
9993. . 0 0007 . 000024 0
.
There are two variables: the zero of voltage compensator Av and the crossover frequency of voltage loop fc. Assume the phase margin of voltage loop is 80 degrees.
⎪⎩
From (4-38), we have derived:
⎪⎪
And so on, the parameters of the digital voltage compensator can be found by MATLAB.
(4-40)
The bandwidth of this control system will be about 9 Hz. Therefore, the digital voltage compensator transfer function is
1 .
Fig. 4.9 compares the frequency responses of voltage loop gain between circuit sweep and the transfer function calculating.
10-1 100 101 102 -50
0 50
Magnitude (dB)
10-1 100 101 102
Phase (Degree)
Frequency (Hz)
Circuit Sweeps Transfer Function
Fig. 4.9. Comparing frequency responses of loop gain between circuit sweeps and transfer function.
4.2.2 Design of Digital Notch Filter
From the result of previous section, the effect of the output voltage ripple induces lower voltage loop bandwidth. This paper adds a digital notch filter to eliminate the ripple effect on the input line current THD as shown in Fig. 4.10 [25]-[28]. The transfer function of a second-order notch filter in s-domain can be expressed as
.
When the notch filter center frequency ωo = λ, there is no signal transmission through the filter. And b is the 3 dB rejection bandwidth. Using the bilinear transformation to transfer N(s) to z-domain as follow
2
The center frequency of the notch filter in z-domain can be obtained by setting the value of magnitude for zero, which yields the magnitude of the notch filter is dropped to 3 dB from the dc value of the notch filter in z-domain are found as follow
2
Note that the frequencies ω1 and ω2 where the magnitude is determined by
2
where Ω is the 3 dB bandwidth of the notch filter. From (4-45) and (4-46), the λ and b can be determined as
2 )
The center frequency of notch filter is placed at the double line frequency, which is 120 Hz (2ωline = ωo), and the 3 dB bandwidth of the notch filter sets at 50 Hz. This thesis sets the parameters of the notch filter, which are λ = 0.038 and b = 0.159, to satisfy the requirement. Fig. 4.11 and Fig. 4.12 show the input line current without and with notch filter, the load variation sets a step current load, which changes from 50 % to 100 %. In Fig. 4.11, the output voltage transient time is 40 ms and the input line current THD is 20 %. When the notch filter is applied in the voltage loop, the transient time still maintains at 40 ms but the input line current THD can be improved down to 6 % as shown in Fig. 4.12.
Notch Filter N(z)
Notch Filter N(z)
Fig. 4.10. Block diagram of the digital voltage control loop with notch filter.
34 ms 2.7 V
34 ms 2.7 V
Fig. 4.11. The transient response of output voltage and input line current waveform without notch filter, load changes from 50 % to 100 %.
33 ms 2.5 V
33 ms 2.5 V
Fig. 4.12. The transient response of output voltage and input line current waveform with notch filter, load changes from 50 % to 100 %.
4.2.3 Design of Load Adaptive Gain Scheduling
From previous section discuss, added notch filter can increase voltage loop bandwidth and maintain the input line current low THD and high PF. But on different load conditions, the dynamic characteristics of the boost AC-DC converter have also different. Therefore, an adaptive control scheme is given to address different load variations for maintaining a stable and fast dynamic response. The load adaptive control scheme applies a look-up table to
estimate the modified gain, and the modified gain is determined by using linear interpolation
The look-up table of the modified factor of the digital PIcontroller is shown in Table 4.1 The digital PI controller with load adaptive gain scheduling can be modified as
1 .
Fig. 4.13 and Fig. 4.14 show the transient responses of output voltage without and with the load adaptive control scheme. In Fig. 4.13, the transient time is 43 ms from 10 W to 50 W and 30 ms from 60 W to 100 W, these reveal when without load adaptive control scheme, dynamic response of the output voltage is different at different load conditions change. Applied the adaptive control scheme, Fig. 4.14 shows the transient time is maintained 30 ms from 10 W to 50 W and 30 ms from 60 W to 100 W, the dynamic responses become optimal at different load conditions change after adding the load adaptive scheme.
1.88 1.9 1.92 1.94 1.96 1.98 2 397
398 399 400 401
Time (sec)
Output Voltage (V)
Load from 10 W to 50 W
1.88 1.9 1.92 1.94 1.96 1.98 2
396 397 398 399 400 401 402
Time (sec)
Output Voltage (V)
Load from 60 W to 100 W
43 ms
30 ms
Fig. 4.13. The transient responses of output voltage without load adaptive gain adjustment, load changes from 10 W to 50 W and 60 W to 100 W.
1.88 1.9 1.92 1.94 1.96 1.98 2
397 398 399 400 401
Time (sec)
Output Voltage (V)
Load form 10 W to 50 W
1.88 1.9 1.92 1.94 1.96 1.98 2
396 397 398 399 400 401 402
Time (sec)
Output Voltage (V)
Load form 60 W to 100 W
30 ms
30 ms
Fig. 4.14. The transient responses of output voltage with load adaptive gain adjustment, load changes from 10 W to 50 W and 60 W to 100 W.