Data Bank Design v2 (Interleaved Data Bank)

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In data bank design v1, there are some access situation cases. These access cases make the address control complex. And the output bit of each data bank is wide. In data bank design v2, we want to design a simpler data bank and the address control is also simpler.

Basic idea of interleaved data bank is that the requested texels of bilinear filtering are in different data banks. Output bit of each data bank is one texels. This concept of interleaved data bank is that from [11], Igehy proposed a texture data organization which use 6D placement. We follow this concept to design our interleaved data bank.

The proposed data bank v2 is shown Fig. 3-11. The extra circuit called address control is to switch the texel addresses to the correct corresponded data bank, we will introduce it at section 3.2.2.

Fig. 3-12 shows that the texels are interleaved mapped in data bank. The left part is the texture and number is the coordinate of texels. The right part is the texels mapped data bank number. We can find that in each 2×2 tile, texels in the tile are from different data banks, so that one bilinear filtering can fetch the four texels from four data banks in one cache access. The difficulty of interleaved data bank is that how we map the texels in data bank interleaved by addresses. To do that, we analyze each texture placement methods introduced in chapter 2 and to find the mapping method to map texels in data bank, which will be introduced at next section.

Fig. 3-11 Data bank design v2: interleaved data bank

Fig. 3-12 texel mapping in data bank

3.2.1 Address Mapping in Cache

For mapping address to cache, the mapping rule is like the rule introduced in data bank design v1. Consider the texture placement tile size which is , the texel with address

NxN

A is in data bank A[log₂(N)+3][3] and position in data bank is the remain bits of line offset.

First, we use texture placement tile size 2×2 (Ex: 4D_2×2, 6D_N×N_2×2, RZ) as example. Texel which its address is A , the data bank id is

( ) and offset in data bank is the remainder bits of line offset. The data bank id and offset in data bank field in texel address are shown in Fig. 3-13

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Fig. 3-13 Data bank id and offset in data bank field in address with 2×2 tile size

Use this rule to map a texture in cache. An example is shown in Fig. 3-14, texture placement method is RZ and cache line size is 64 bytes. The number above is the address of texel and number below is the binary code of the address. We find that use the boldface and italic numbers of binary code as data bank id, each texel in 2×2 tile can be placed in different data banks.

Fig. 3-14 Texel mapping in interleaved data bank which tile size is 2×2 and cache line size is 64 byte

Fig. 3-15 is the address mapping in cache which is following the example shown in Fig. 3-14. Texels which addresses are 0, 4, 8, and 12 are placed in the same data bank (DB0) because they have the same data bank id (00). Texels which addresses are 1, 5,

9, and 13 are placed in the same data bank (DB1) because they have the same data bank id (01), so are other texels.

Fig. 3-15 Address mapping in interleaved data bank, which tile size is 2×2 and cache line size is 64 bytes

We use tile size is 4×4 as another example. From the mapping rule, texel with address A is at data bank A[log₂(4)+3][3] ( ) and the position in data bank is the remainder bits of line offset. Fig. 3-16 shows the data bank id and position in data bank field in address which texture placement tile size is 4×4.

] 3 ][

5 [ A

Fig. 3-16 Data bank id and offset in data bank field in address with 4×4 tile size

The concept is that u direction of texture coordinate place four texels then v direction of texture coordinate place one texel. It can be seen as that the u direction offers two bits then v direction offers one bit. So, we can use this concept to place each 2×2 tile of texture in data bank interleaved which texture placement tile size is 4×

4. The data bank id is the boldface and italic number of the binary code of address in the Fig. 3-17.

Fig. 3-17 Texel mapping in interleaved data bank with 4×4 tile size

Fig. 3-18 shows an example of address mapping in data bank which is following the example shown in Fig. 3-17. Assume cache line size is 64 bytes (16 texels). Texels with address is 0, 2, 8, and 10 are placed in the same data bank (DB0). The texels with address 1, 3, 9, and 11 are placed in the same data bank (DB1) and so on. From Fig.

3-18 we can find that the requested texels are in different data banks for each 2×2 texels.

Fig. 3-18 Address mapping in interleaved data bank, which tile size is 4×4 and cache line size is 64 bytes

Use the rule to find other tile size interleaved mapping method. Tile size is 8×8 uses third and fifth bits of address to be data bank id and so on.

The constraint of the interleaved data bank is that the cache line size has to be the smallest tile size at least. If the cache line size is small than tile size, the data in a line are not continuous. For example, if cache line size for tile size is 4×4 is 16 bytes, it means that a line is texels with address 0, 1, 4, 5 and the next line is texels with

address 2, 3, 6, 7. At this situation, if cache is missed, memory may have to transmit several times. This makes miss plenty be worse.

3.2.2 Address Control

The function of address control in data bank design v2 is to switch the address to corresponded data bank. It receives addresses from the address translation array and then switches the addresses to the corresponded data bank. There are four cases which are address mapping data bank of bilinear filtering, shown in Fig. 3-19. First, see the above part, four texels masked by square are the requested texels of bilinear filtering.

The below part is address control how to switch the addresses to the corresponded data bank.

Fig. 3-19 Cases of switching address to corresponded data bank.

By analysis of the four cases, we find the situation that the address from ATi is sent to DBj (i and j are 0~3), and the address from ATj is sent to DBi. It can be seen as two of the four addresses change its address. So we use four 4-1 multiplexer to implement address control and the select signal is the data bank field of the address from the

corresponded AT. The implementation circuit of address control is shown in Fig. 3-20.

Fig. 3-20 Address control in data bank design v2

3.2.3 Discussion of Interleaved Data Bank

The effect of accessing four data banks in one cache access is waste of dynamic power. But output bit of each data bank is one texels. The energy consumption between these two data bank designs depends on bilinear filtering access parameters.

If requested texels are in one data bank in data bank design v1, the access energy in data bank design v1 is less than data bank design v2. On the other hand, if requested texels are in different data banks, the access energy in data bank design v1 is larger than data bank design v2.