DCache and write buffer operation

The DCache and write buffer configuration of each memory region is controlled by the Ctt and Btt bits in each section and page descriptor in the MMU translation tables. You can modify the configuration using the DCache enable bit in the CP15 control register.

This is called Ccr.

If the DCache is enabled, a DCache lookup is performed for each data access initiated by the ARM9TDMI CPU core, regardless of the value of the Ctt bit in the relevant MMU translation table descriptor. If the required data is found, the lookup is called a cache hit. If the required data is not found, the lookup is called a cache miss. In this context a data access means any type of load (read), store (write), or swap instruction, including LDR, LDRB, LDRH, LDM, LDC, STR, STRB, STRH, STC, SWP, and SWPB.

Accesses appear on the AMBA ASB interface in program order but the ARM9TDMI CPU core can continue executing at full speed, reading instructions and data from the caches, and writing to the DCache and write buffer, while buffered writes are being written to memory through the AMBA ASB interface.

Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM

Table 4-1 describes the DCache and write buffer behavior for each type of memory configuration. Ctt AND Ccr means the bitwise Boolean AND of Ctt with Ccr.

Table 4-1 DCache and write buffer configuration Ctt AND

Ccr Btt DCache, write buffer, and memory access behavior

0^a 0 Noncached, nonbuffered (NCNB).

Reads and writes are not cached. They always perform accesses on the AMBA ASB interface.

Writes are not buffered. The CPU halts until the write is completed on the AMBA ASB interface.

Reads and writes can be externally aborted.

Cache hits never occur under normal operation.^b

0 1 Noncached, buffered (NCB).

Reads and writes are not cached, and always perform accesses on the AMBA ASB interface.

Writes are placed in the write buffer and appear on the AMBA ASB interface. The CPU continues execution as soon as the write is placed in the write buffer.

Reads can be externally aborted.

Writes cannot be externally aborted.Cache hits never occur under normal operation.^b

1 0 Cached write-through mode (WT).

Reads that hit in the cache read the data from the cache and do not perform an access on the AMBA ASB interface.

Reads that miss in the cache cause a linefill.

Writes that hit in the cache update the cache.

All writes are placed in the write buffer and appear on the AMBA ASB interface.

The CPU continues execution as soon as the write is placed in the write buffer.

Reads and writes cannot be externally aborted.

Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM

A linefill performs an 8-word burst read from the AMBA ASB interface and places it as a new entry in the cache, possibly replacing another line at the same location within the cache. The location that is replaced, called the victim, is chosen from the entries that are not locked using either a random or round-robin replacement policy. If the cache line being replaced is marked as dirty, indicating that it has been modified and that main memory has not been updated to reflect the change, a cache writeback occurs.

Depending on whether one or both halves of the cache line are dirty, the write-back performs a 4 or 8-word sequential burst write access on the AMBA ASB interface. The write-back data is placed in the write buffer, and then the linefill data is read from the AMBA ASB interface. The CPU can then continue while the write-back data is written to memory over the AMBA ASB interface.

Load multiple (LDM) instructions accessing NCNB or NCB regions perform sequential bursts on the AMBA ASB interface. Store multiple (STM) instructions accessing NCNB regions also perform sequential bursts on the AMBA ASB interface.

1 1 Cached write-back mode (WB).

Reads that hit in the cache read the data from the cache and do not perform an AMBA ASB interface access.

Reads that miss in the cache cause a linefill.

Writes that hit in the cache update the cache and mark the appropriate half of the cache line as dirty, and do not cause an AMBA ASB interface access.

Writes that miss in the cache are placed in the write buffer and appear on the AMBA ASB interface. The CPU continues execution as soon as the write is placed in the write buffer.

Cache write-backs are buffered.

Reads, writes, and write-backs cannot be externally aborted.

a. If the control register C bit (Ccr) is zero, it disables all lookups in the cache, while if the translation table descriptor C bit (Ctt) is zero, it only stops new data being loaded into the cache. With Ccr = 1 and Ctt = 0 the cache is still searched on every access to check whether the cache contains an entry for the data.

b. It is an operating system software error if a cache hit occurs when reading from, or writing to, a region of memory marked as NCNB or NCB. The only way this can occur is if the operating system changes the value of the C and B bits in a page table descriptor, while the cache contains data from the area of virtual memory controlled by that descriptor. The cache and memory system behavior resulting from changing the page table descriptor in this way is unpredictable. If the operating system has to change the C and B bits of a page table descriptor, it must ensure that the caches do not contain any data controlled by that descriptor. In some circumstances, the operating system might have to clean and flush the caches to ensure this.

Table 4-1 DCache and write buffer configuration (continued) Ctt AND

Ccr Btt DCache, write buffer, and memory access behavior

Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM

The sequential burst is split into two bursts if it crosses a 1KB boundary. This is because the smallest MMU protection and mapping size is 1KB, so the memory regions on each side of the 1KB boundary can have different properties.

This means that sequential accesses generated by ARM922T do not cross a 1KB boundary. This can be exploited to simplify memory interface design. For example, a simple page-mode DRAM controller can perform a page-mode access for each sequential access, provided the DRAM page size is 1KB or larger.

See also Cache coherence on page 4-17.