LDC/STC

Coprocessor Interface

Coprocessor Interface

In Figure 7-2 on page 7-5, four words of data are transferred. The number of words transferred is determined by how the coprocessor drives the CHSDE[1:0] and CHSEX[1:0] buses.

As with all other instructions, the ARM922T processor core performs the main instruction decode off the rising edge of the clock during the Decode stage. From this, the ARM9TDMI CPU core commits to executing the instruction, and so performs an instruction Fetch. The coprocessor instruction pipeline keeps in step with the ARM922T by monitoring CPMREQ, a latched copy of the ARM9TDMI instruction memory request signal InMREQ. Whenever nCPMREQ is LOW, an instruction Fetch is occurring and CPID is updated with the fetched instruction in the next cycle. This means that the instruction currently on CPID enters the Decode stage of the coprocessor pipeline, and that the instruction in the Decode stage of the coprocessor pipeline enters its Execute stage.

During the Execute stage, the condition codes are combined with the flags to determine whether the instruction can be executed or not. The output CPPASS is asserted (HIGH) if the instruction in the Execute stage of the coprocessor pipeline:

• is a coprocessor instruction

• has passed its condition codes.

If a coprocessor instruction busy-waits, CPPASS is asserted on every cycle until the coprocessor instruction is executed. If an interrupt occurs during busy-waiting, CPPASS is driven LOW, and the coprocessor stops execution of the coprocessor instruction.

Another output, CPLATECANCEL, is used to cancel a coprocessor instruction when the instruction preceding it caused a Data Abort. This is valid on the rising edge of CPCLK on the cycle after the first Execute cycle of the coprocessor instructions.

CPLATECANCEL is only asserted during the first Memory cycle of the execution of coprocessor instructions.

On the falling edge of the clock, the ARM922T processor core examines the coprocessor handshake signals CHSDE[1:0] or CHSEX[1:0]:

• if a new instruction is entering the Execute stage in the next cycle, it examines CHSDE[1:0]

• if the coprocessor instruction currently in Execute requires another Execute cycle, it examines CHSEX[1:0].

Coprocessor Interface

The handshake signals encode one of four states:

ABSENT If there is no coprocessor attached that can execute the coprocessor instruction, the handshake signals indicate the ABSENT state. In this case, the ARM9TDMI processor core takes the undefined instruction exception.

WAIT If there is a coprocessor attached that can execute the instruction but not immediately, the coprocessor handshake signals must be driven to indicate that the ARM9TDMI processor core must stall until the coprocessor can catch up. This is known as the busy-wait condition.

In this case, the ARM9TDMI processor core loops in an IDLE state, waiting for CHSEX[1:0] to be driven to another state, or for an interrupt to occur. If CHSEX[1:0] changes to ABSENT, the undefined instruction exception is taken. If CHSEX[1:0] changes to GO or LAST, the instruction proceeds as described below.

If an interrupt occurs, the ARM9TDMI processor core is forced out of the busy-wait state. This is indicated to the coprocessor by the CPPASS signal going LOW. The instruction is restarted at a later date. Therefore the coprocessor must not commit to the instruction (change any of the coprocessor states) until it has seen CPPASS go HIGH, and the handshake signals indicate the GO or LAST condition.

GO The GO state indicates that the coprocessor can execute the instruction immediately, and that it requires another cycle of execution. Both the ARM9TDMI processor core and the coprocessor must also consider the state of the CPPASS signal before actually committing to the instruction.

For an LDC or STC instruction, the coprocessor instruction must drive the handshake signals with GO when two or more words still have to be transferred. When only one more word is required, the coprocessor must drive the handshake signals with the LAST condition.

In phase 2 of the Execute stage, the ARM9TDMI processor core outputs the address for the LDC/STC. Also in this phase, DnMREQ is driven LOW, indicating to the memory system that a memory access is required at the data end of the device. The timing for the data on CPDOUT[31:0] for an LDC, and CPDIN[31:0] for an STC, is as shown in Figure 7-2 on page 7-5.

LAST An LDC or STC can be used for more than one item of data. If this is the case, possibly after busy waiting, the coprocessor must drive the coprocessor handshake signals with a number of GO states and, in the penultimate cycle, with LAST. The LAST indicating that the next transfer is the final one. If there is only one transfer, the sequence is

Coprocessor Interface

7.2.1 Coprocessor handshake encoding

Table 7-1 shows how the handshake signals CHSDE[1:0] and CHSEX[1:0] are encoded.

If you do not attach a coprocessor to the ARM922T, then the handshake signals must be driven with ABSENT.

If you attach multiple coprocessors to the interface, the handshaking signals can be combined by ANDing bit 1, and ORing bit 0. In the case of two coprocessors that have handshaking signals CHSDE1, CHSEX1 and CHSDE2, CHSEX2 respectively:

CHSDE[1]<= CHSDE1[1] AND CHSDE2[1]

CHSDE[0]<= CHSDE1[0] OR CHSDE2[0]

CHSEX[1]<= CHSEX1[1] AND CHSEX2[1]

CHSEX[0]<= CHSEX1[0] OR CHSEX2[0].

Consequently, if the coprocessor does not recognize a coprocessor instruction, it must drive CHSDE[1:0] and CHSEX[1:0] with ABSENT.

Table 7-1 Handshake encoding

State [1:0]

ABSENT 10

WAIT 00

GO 01

LAST 11

Coprocessor Interface