A.2 Error Bound Analysis of GIT Based Steady State Temperature Formulation
B.1.1 Derivation of Evaluating Algorithm for the Projection Coe fficient of
Expressing ψL(ηL) = cTLmηL + β2ηTLGLmηL and ψtox(ηtox) = cTtoxmηtox + β4ηTt
oxGtoxmηtox and em-ploying the independent property of ηLand ηtox, we have
EnΦk(ξ)eψL(ηL)eψtox(ηtox)o = E nΦkL(ηL)eψL(ηL)o
EnΦktox(ηtox)eψtox(ηtox)o . (B.10)
The computation formulae of EnΦkL(ηL)eψL(ηL)o
and EnΦktox(ηtox)eψtox(ηtox)o
can be derived by using the deviation similar with equations (B.7)–(B.9). Consequently, the evaluating algorithm shown in Figure 3.9 is concluded.
Appendix C
Proof of Proposition 1
First, we introduce a lemma for thermal conductance matrices G= Gh+ ∆G and Gh. Lemma 3. Both conductance matrices G and Ghare positive definite.
Proof. Since G and Gh are conductance matrices, they are symmetric matrices that satisfy the irreducible diagonal dominant property [111] and have positive real diagonal entries. Hence, G
and Ghare positive definite [112].
Based on Lemma 3, we have the following lemma.
Lemma 4. The absolute value of each eigenvalue of G−1h ∆G is less than 1.
Proof. Let λ be an eigenvalue of G−1h ∆G, and y be its corresponding eigenvector. Considering yT(Gh+ ∆G)y, we have
yT(Gh+ ∆G)y = yTGh(I+ G−1h ∆G)y
= (1 + λ)yTGhy. (C.1)
From Lemma 3, we have yT(Gh+ ∆G)y > 0 and yTGhy> 0. Therefore, λ > −1.
Since a 3-D IC has a nonzero thermal conductivity value at any position, (Gh−∆G) is also a thermal conductance matrix. Applying a similar derivation to yT(Gh− ∆G)y > 0, we have λ < 1. Therefore, |λ| < 1, and Lemma 4 is concluded.
To complete the proof of Proposition 1, we require the following proposition stated in [113].
Proposition 2. Let A ∈ Fn×n, and assume thatspard (A) < 1. Then, the seriesP∞
i=0Aiconverges absolutely, and
(I − A)−1 =
∞
X
i=0
Ai, (C.2)
where Fn×nis the set of n × n real or complex matrices, andspard (A) is the maximum absolute eigenvalue of A.
With setting A= −G−1h ∆G in equation (C.2) and using Lemma 4, we have
T= (Gh+ ∆G)−1p= Gh(I+ G−1h ∆G)p =X∞
i=0(−1)i(G−1h ∆G)iG−1h p. (C.3) Consequently, Proposition 1 is concluded.
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Biography
Pei-Yu Huang received the B.S. degree in electrical engineering from the National Taiwan University of Science and Technology, Taiwan, in 2004. From 2004, he is pursuing the Ph.D. degree in the Department of Communication Engineering. His research interests include computer-aided design of integrated circuits, thermal analysis, thermal optimization technique, and power grid analysis.
Publication List
Journal:
[1] Pei-Yu Huang and Yu-Min Lee, “Full-chip thermal analysis for the early design stage via generalized integral transforms”, IEEE Transactions on Very Large Scale Integration Systems, vol. 17, no. 5, pp. 613–626, 2009.
[2] Pei-Yu Huang and Yu-Min Lee, “Hierarchical Power Delivery Network Analysis via Bipartite Markov Chains”, International Journal of Electrical Engineering (IJEE), vol. 16, no. 2, pp. 121-132, 2009.
International Conference:
[1] Pei-Yu Huang, Chi-Wen Pan and Yu-Min Lee, “On-Chip Statistical Hot-Spot Estimation Using Mixed-Mesh Statistical Polynomial Expression Generating and Skew-Normal Based Moment Matching”, Accepted by Asia South Pacific Design Automation Conference (ASPDAC), 2012.
[2] Huai-Chung Chang, Pei-Yu Huang, Ting-Jung Li, and Yu-Min Lee, “Statistical Electro-Thermal Analysis with High Compatibility of Leakage Power Models”, International SoC Conference (SOCC), pp. 139-144, Sept. 2010.
[3] Pei-Yu Huang, Jia-Hong Wu and Yu-Min Lee, “Stochastic Thermal Simulation Considering Spatial Correlated Within-Die Process Variations”, Asia South Pacific Design Automation Conference (ASPDAC), pp. 31-36, 2009.
[4] Shih-An Yu, Pei-Yu Huang and Yu-Min Lee, “A Multiple Supply Voltage Based Power Reduction Method In 3-D ICs Considering Process Variations And Thermal
[4] Shih-An Yu, Pei-Yu Huang and Yu-Min Lee, “A Multiple Supply Voltage Based Power Reduction Method In 3-D ICs Considering Process Variations And Thermal