Due to the shrinking of device geometries, it is more difficult to control the physical device pa-rameters. The growing variability of physical device parameters, such as the effective channel length and the gate oxide thickness, can induce considerable leakage power fluctuations. Since the on-chip temperature is transformed from the on-chip power, the fluctuations of on-chip leak-age powers lead to the thermal simulation with nominal leakleak-age powers is no longer effective to predict the on-chip temperature. In addition, since the leakage powers depend on the operating temperature, the temperature-power coupling effect occurs. This leads the electro-thermal anal-ysis to be more concerned for ensuring the thermal reliability. In this chapter, we will introduce the temperature and process variations issues of two major leakage powers, gate tunneling and subthreshold leakage powers, and highlight its impacts on the on-chip temperature.
1.2.1 Subthreshold Leakage Current
The subthreshold leakage current of a MOSFET is defined as the conduction current between source and drain in “OFF” state. The subthreshold leakage current of the MOSFET can be
SubthresholdLeakage Current (μA)
L(nm)
tox(Åm)
Gate Tunneling Leakage Current (μA)
10
Figure 1.3: The temperature and process variation dependencies of subthreshold and gate tun-neling leakage currents of a NAND gate at 65nm technology node. (a) The temperature and process variation dependencies of subthreshold leakage current. (b) The temperature and pro-cess variation dependencies of gate tunneling leakage current. Here, L is the device channel length, and its unit is nm. toxis the oxide thickness, and its unit isA m.o
written as [16, 17]
and Vgs is the gate-to-source voltage, Vth is the threshold voltage, n is the subthreshold swing factor, k is the Boltzmann’s constant, T is the operating temperature, q is the charge of an electron, Vds is the drain-to-source voltage, µ0 is the low field carrier mobility, Cox is the gate oxide capacitance, W is the channel width and L is the channel length.
According to the above model, the subthreshold leakage current exponentially depends on the operating temperature. Although the exponential dependencies for channel length L and oxide thickness toxare not shown in equation (1.10), the subthreshold leakage current exponen-tially depends on L and tox because Vth is a function of these physical device parameters [18].
To illustrate the dependencies of the temperature, the channel length and the oxide thickness for the subthreshold leakage current, the HSPICE simulation result for a NAND gate at 65nm
1.2.2 Gate Tunneling Leakage Current
According to quantum mechanics, carriers have a finite probability to tunnel through the gate oxide. The current generated by these carriers is so-called the gate tunneling leakage current and have been characterized by BSIM4 gate tunneling model [19]. For describing the major parameters that affect the gate tunneling leakage current, BSIM4 model for the gate tunneling leakage current is simplified as [16, 20]
Ig= (A · C)(W · L) exp −B · tox
Vgs
α
!
, (1.11)
where A = q3/8πhφb, C = (Vgs/tox)2, W is the channel width, L is the channel length, B = 8π√
2moxφ3/2b /3hq, toxis the oxide thickness, Vgs is the gate-to-source voltage, α is a parameter with range from 0.1 to 1 depending on the voltage drop across the oxide (a typical value is 0.22867), h is the Planck’s constant, mox is the effective mass of electron/hole, q is the charge of an electron, and φb is the barrier height for electrons/holes in the conduction/valance band.
The value of φbis 3.1eV for electron and 4.5eV for hole.
According to the above empirical model, the gate tunneling leakage current negatively and exponentially depends on the oxide thickness. When the value of the oxide thickness is larger than 20˚Am, the gate tunneling leakage current is relatively small comparing with other leakage currents, such as the subthreshold leakage current. However, the gate tunneling leakage current increases 2.5× for 1˚Am decrease of oxide thickness. This results in over 30× increase of the gate tunneling leakage current per technology generation [21]. Therefore, the gate tunneling leak-age current becomes an important factor in the advanced technology node, e.g the sub-100nm technology node [22]. Furthermore, although the dependencies of the temperature are not ex-plicitly shown in equation (1.11), based on the SPICE simulation with BSIM4 model [23], the gate tunneling leakage current weakly depends on the temperature. To illustrate dependencies of the temperature, the channel length and the oxide thickness for the gate tunneling leakage current, the HSPICE simulation result for a NAND gate at 65nm technology node is shown in Figure 1.3(b).
1.2.3 Leakage Powers Inducing Electro-Thermal (Temperature-Power) Coupling E ffect
Generally, the on-chip power consumption Pchipconsists of dynamic power and leakage power, and it can be calculated by [24]
Pchip= SactCtotalVdd2 f + VddIleak, (1.12)
where Sact is the average switching activity of gates, Ctotal is the total load capacitance of gates, Vdd is the supply voltage, f is the operating frequency and Ileak is the total leakage current of gates.
In the right hand side of equation (1.12), the first term is the dynamic power induced by the charging and discharging currents to the load capacitance of gates, and the second term is the leakage power induced by the leakage currents of gates. As mentioned in sections 1.2.1 and 1.2.2, the leakage powers exponentially depend on the operating temperature, and the on-chip leakage power will catch up with the on-on-chip dynamic power beyond the 90nm technology node [24,25]. On the other hand, the on-chip temperature is transformed from the on-chip power consumption. Therefore, electro-thermal (temperature-power) coupling occurs, and it induces the thermal reliability issues in the modern VLSI designs. For example, thermal runaway [26]
may happen if the elector-thermal coupling is not well concerned during the package and the cooling system design.
The mechanism of electro-thermal coupling is exhibited in Figure 1.4. First, with an initial on-chip temperature, the initial on-chip power consumption is obtained. Based on the zeroth law of thermodynamics [27], surplus powers, which can not be dissipated by the package and the cooling system, will transform into heat for achieving the equilibrium of the generating and dissipated powers; therefore, the on-chip temperature increases. On the contrary, as the power dissipation capacity of the package and the cooling system is larger than the generating power of the chip, the on-chip temperature decreases. Because the leakage power consumption depends on the temperature, the total power consumption will change after the temperature is updated. With repeating the above mechanism, if the equilibrium of the generating and dissi-pated powers of the chip can be achieved, stable on-chip temperature and power consumption
Total Power = Dynamic Power + Leakage Power
Power Dissipation of the Package and the Cooling System
Point of Thermal Runaway Occurring
Thermal Runaway
Stable Temperature TS
Temperature Temperature T1Initial
Initial Temperature T2 Total On-Chip
Power Consumption
Figure 1.4: The mechanism of electro-thermal coupling.
are accomplished. On the contrary, if the thermal equilibrium can not be achieved1, the chip thermally runs away. For example, as shown in Fig 1.4, the red curve indicates the generating power of the chip operating at different temperatures. The straight line indicates the maximum power that can be dissipated by the package and cooling system at different operating temper-atures. Given an initial temperature T 1, the stable operating temperature T S can be achieved after electro-thermal coupling is proceeded. On the other hand, if the initial temperature is T 2, the thermal runaway occurs.
As the example illustrating, it is important to consider the electro-thermal coupling to ensure the thermal reliability of the circuit.
1.2.4 Variations of Physical Device Parameters
The shrinking of device geometries has leaded to considerable variations of physical device pa-rameters. As mentioned in sections 1.2.1 and 1.2.2, leakage powers are sensitive to the physical device parameters, such as the channel length and the oxide thickness. Therefore, the variations of physical device parameters will induce considerable fluctuations of the leakage powers. As shown in Figure 1.5, Borkar et. al. [2] have pointed out that 30% process variations can cause about 20× leakage power fluctuations. Because of the electro-thermal coupling, this will result
1The curves of the generating power of the chip and dissipated power of the package and the cooling system do not have intersection points, or the initial operating temperature is not well chosen [26]
Figure 1.5: Parameter variations impacts on the leakage currents (reprinted from [2]). Here, the y-coordinate indicates the normalized occurrence frequency of the value of the device channel length, and the x-coordinate indicates the normalize value for the subthreshold leakage currents (Isb).
in considerable fluctuations of the on-chip temperature and the temperature inducing leakage power fluctuations. Therefore, under process variations, the on-chip temperature and leakage power should be treated statistically, especially for the leakage power dominated technology.