Design of Data Interface

Since a practical FFT processor shall receive serial in data in reality, N input samples have to be temporarily stored in a buffer before FFT operations are started.

Similarly, FFT output data should be recorded in a memory buffer for the following channel equalization or demodulation operations.

Fig 5.5 shows three popular memory arrangement schemes that properly handle those input and output data. One scheme is inserting an input RAM buffer that per-forms serial to parallel converter, and an output RAM buffer that preserve the previ-ous FFT results. Another is using three identical memory blocks, where one of them alternately acts as PE’s data memory and the remaining two act as the input buffer and output buffer respectively. The third scheme [51] is reading the input RAM buffer and performing the first-stage FFT before the guard interval has passed. Furthermore, during the final-stage FFT operation, the computational results are written to the out-put RAM for the following demodulation operations, instead of the main RAM for intermediate data read and write.

In the structure of Fig. 5.5(a), there exists clock rate difference between the front-end function modules and FFT processor, because of the rate mismatch between the input data rate N and the total operation count O(NlogrN). Namely, the intermedi-ate data memory is accessed with a faster PE’s clock rintermedi-ate, while the input buffer is accessed with a slower front-end system clock rate. Similarly, the output buffer is ac-cessed with another back-end system clock rate. However, when an FFT computation has been completed, we have to directly transfer the N-point output data from the in-termediate data memory to output buffer in a short time and then load the next N-point

rate is a critical issue during the input and output data transfers, and the input (output) buffer has to be driven by another clock rate which is faster than the front-end (back-end) system clock rate. This kind of clock difference isn’t too hard to handle with state-of-art VLSI technology. But the direct input and output data transfers with-out memory remapping is inefficient.

Input buffer (N-word RAM)

Input data Intermediate

data memory (N-word RAM)

PE

Access

Output buffer (N-word RAM)

Load Load Output data

(a) The 1st data interface structure for FFT PE

RAM_ 1 (N-word RAM)

RAM_2 (N-word RAM)

PE Access

RAM_3 (N-word RAM)

Switch Switch

Access

Access Access

Switch Input data

Load

Output data

Load

(b) The 2nd data interface structure for FFT PE

Input buffer (N-word RAM)

Input data Intermediate

data memory (N-word RAM)

PE Access

Output buffer (N-word RAM)

Output data

Read Write

(c) The 3rd data interface structure for FFT PE Fig. 5.5 Data interface structures for FFT PE

In the interface structure of Fig. 5.5(b), three identical memory blocks take turns in serving as input buffer, PE’s data memory, or output buffer. Namely, when one memory block is loading the next N-point input data, another memory block provides current N-point FFT data executed by PE, and the other holds the previous FFT result for back-end function module. When the next symbol period begins, memory blocks change their roles and repeat the mentioned process. For instance, the memory block which stores the input data will act as PE’s data memory next time. However, clock of the memory block is synchronous to front-end function modules when working as in-put buffer, while it should be synchronous to the faster FFT processor when working as PE’s data memory. As a result, those memory blocks have to be driven by different clocking systems. This status is similar to the first interface structure, but without di-rectly transference.

In the interface structure of Fig. 5.5(c), the N input data collected in the input buffer will be read to PE to perform the first-stage FFT operation and then written back to the PE’s intermediate data memory before the guard interval has passed.

Therefore, we don’t have to execute the copy operations between data memory and input buffer. Similarly, the results of the last-stage FFT operation are written to output buffer instead of PE’s data memory. However, for the proposed CORDIC-based FFT PE, we need more PE operation cycles than the multiplier-based FFT PE. Conse-quently, in order to complete the required computation within the guard interval, we have to speed up the operation clock rate of CORDIC-based PE, especially for DVB-T and 802.16. Therefore, we don’t adopt this structure.

By employing the interface structure of Fig. 5.5(b), the total required number of CORDIC iteration operation with respect to various OFDM communication systems is shown in Table 5.2. In this table, 802.16 is the most demanding in speed issue. If

cover all the OFDM communication systems listed in Table 5.2.

Table 5.2 The required operation counts and clock rates of the proposed

CORDIC-based PE to various OFDM communication specifications (output precision is 12-bit)

Standards Symbol duration Total PE opera-tion cycles

Cycle duration (ns)

Clock rate (MHz) 8K mode

(924µs) 68252 924/68252 = 13.5 73.8

DVB-T

2K mode

(231µs) 14472 231/14472 = 15.9 62.6

2048

(1246µs) 14472 1246/14472 =

86.1 11.6

1024

(623µs) 5204 623/5204 = 119.7 8.3

512

(312µs) 3092 312/3092 = 101 9.9

DAB

256

(156µs) 1232 156/1232 = 126.6 7.9

802.16 2048

(105.6µs) 14472 105.6/14472 = 7.3 137

Chapter 6 Conclusion

In this thesis, we propose an in-place memory-based variable-length FFT proc-essor architecture, which is suited for multi-mode and multi-standard OFDM systems, including 802.16a, DAB, and DVB-T. The design is featured with the variable-length data address generator which simplifies the original area-consuming barrel-shifter based designs with a few simpler multiplexer-based addressing functions. Further-more, we propose an efficient twiddle factor generator, which has the merit of low area complexity and high speed. Analysis and simulations show that it is favorable over the existing twiddle factor generators for practical FFT operations. The proposed design is mainly suitable for the situations where FFT lengths are long and adjustable, as required by the multi-mode and multi-standard operations defined in the mentioned systems. Finally, we proposed a new CORDIC algorithm which reduces iteration number significantly. It is achieved by combining several design techniques, including efficient high radix rotation scheme, angle encoding, leading-one bit detection, and on-line variable factor compensation. Since the biggest advantage of CORDIC-based FFT is that the twiddle factor generator can be eliminated, we replace the conven-tional complex multiplier and look-up table approach with CORDIC-based butterfly rotation operations.

The FFT core is currently under EDA realization and will be silicon implemented finally. In the future, we will emphasize on the integration into the OFDM baseband systems.

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