Design of Kelvin probes to measure the bump resistance

4.3.1 Results and discussion

Kelvin structures have been used to measure via or contact resistance in Al and Cu interconnect for over twenty years, in which four electrical terminals are employed to measure the contact resistance [68, 69]. The geometrical effect of the contact resistance has been investigated by Natan et al [70]. Liu et al. investigated the electrical resistance of the solder joints, but the current crowding effect was not considered [71]. Electromigration has become an important reliability issue for flip-chip packages due to the continuous shrinking of the solder joints [7,72].

Although the bump resistance may not be a critical issue for signal delay consideration, it can be used to monitor the failure of electromigration test. Recently, many researchers have been using bump resistance changes to monitor electromigration behavior [73-75]. Gee et al. has designed this structure to measure bump resistance in ball grid array during EM [73]. Ebersberger et al. used it to monitor the failure of electromigration in flip-chip solder joints [75]. However, no literature has been found on measuring the bump resistance.

In addition, from the scientific point of view, the bump resistance may be of interest, since serious current crowding occurs in the solder joints, and the joint comprises several materials. Compared with Al and Cu interconnects, the dimension

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of the solder joints is quite large. Therefore, there are several ways to design Kelvin bump structure. However, no significant effort has been made on the measurement and modeling of the bump resistance. The crowding effect on bump resistance has not been studied. In this part of study, we measured the bump resistance by Kelvin structure and employed the 3D finite element modeling to investigate the geometrical effect of bump resistance. This study provides a deeper understanding of the bump resistance in flip-chip solder joints.

We have designed and fabricated Kelvin structure for the flip-chip solder joints which are provided by Megic. Figure 4-9 (a) shows the plan-view schematic for the structure. The test structure consisted of four bumps, in which Al trace connected them together. Al trace was 1.5 μm thick and 100 μm wide. The pitch for the solder joints was 1mm. Six Cu lines in the FR5 substrate connected to the four bumps, and they were labeled as node 1 through 6, as shown in the figure. The dimension of the Cu lines was 30 μm thick and 100 μm wide. The bump connected to the node 3 and node 6 was used to investigate the geometrical effect of bump resistance. Through these six Cu lines, various experimental setups can be performed to measure the bump resistance for Bump 2. In this study, four approaches were adopted to measure the bump resistance. The experimental setup for the first approach was shown in Figure 4-9 (b). The current was applied through nodes 1 and 2, and the voltage drop was

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monitored through nodes 4 and 5. This approach measures the voltage drop on the left-hand side of the bump. The second experimental setup is illustrated in Figure 4-9 (c), in which the current was applied through nodes 1 and 4, and the voltage change was examined using nodes 2 and 5. For this approach, the voltage drop across the diagonal of the bump was measured. The third approach is shown in Figure 4-9 (d), current was applied through nodes 1 and 2, and the voltage difference was measured through nodes 3 and 5. The fourth approach measured the voltage drop across nodes 5 and 6 when current was applied through nodes 1 and 2, as depicted in Figure 4-9 (e).

Surprisingly, the measured bump resistance was much lower than that expected for the four approaches shown in Figures 4-9 (b) and (e). Figure 4-10 shows the typical bump resistances as a function of temperature up to 150 °C for the four approaches. For bump resistance measured by approach 1, the value was only 0.89 mΩ at room temperature. The resistance increased with the increase in temperature, and it was attributed to the TCR. If we assume the TCR to be linear, the estimated TCR for the solder joint was 5.1 × 10^-3 K^-1. The measured bump resistance comprised the contribution from Al, Cu, Ni, Sn and Pb materials. Therefore, the TCR may be the combination of the above materials. The TCR values for the bulk Al, Cu, Ni, Sn, and Pb are 4.2, 4.3, 6.8, 4.6, and 4.2 × 10^-3 K^-1, respectively. Hence, the measured TCR seems to be quite reasonable. The measured bump resistance for the

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same bump was 0.87, 0.96, 0.94 mΩ at room temperature for the second, third, and fourth approaches, respectively. The bump resistances measured by approaches 3 and 4 are slightly larger than those by approaches 1 and 2. The temperature dependence of bump resistance was quite close to that measured by the first approach. The estimated TCR values are 4.4, 4.3, and 4.9 for the three approaches, respectively.

To examine the current and voltage distribution in the solder joints, 3D simulation was performed to provide more understanding of the effect of current crowding on the bump resistance measurement. Figure 4-11 (a) shows the current density distribution in the solder joints upon applying 0.2 A current. The current crowded into the solder bump in the vicinity of the entrance of Al trace, and only a small amount of current flows in the opposite side of the joint. Figure 4-11 (b) illustrates the voltage distribution in the solder joints. Since the resistance of the Al trace was much larger than that of the solder joints due to its smaller cross-section, most of the voltage dropped in the Al trace. Figure 4-11 (c) depicts the cross-sectional view along the YZ plane in Figure 4-11 (b). Apparently, voltage drop mainly occurred at the left-hand side of the bump, which was the current crowding region. The voltage drop on the left-hand side was approximately 9 times larger than that on the right-hand side. This may cause large variation in the measurement of bump resistance. Hence, the measured voltage strongly depends on the layout of the Kelvin

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structure.

To investigate the geometry effect of the bump resistance, voltage at various positions were examined in the solder joints. Figure 4-11 (d) shows the voltage distribution in the solder joint, excluding Al trace and Cu line. Two positions, 1 and 5 in the chip side were labeled. On the substrate side, positions 2, 3, 4, and 6 were labeled. The definition of the positions matched the six nodes in Figure 4-9 (a). When the current was applied through nodes 1 and 2, the voltages in the six positions were examined. The results are listed in Table 4-1. The voltages in the chip side were obtained by averaging the voltages in the junction of Al trace and Al pad. The junction area was approximately 110 μm × 1.5 μm. For voltages in the substrate side, they were estimated by averaging the voltages in the junction of Cu line and Cu pad.

The junction area was approximately 110 μm × 30 μm. It was found that the voltage drop across positions 1 and 2 was 1.54 mV, whereas it was only 0.15 mV across positions 4 and 5 (First approach), and it was 0.17 mV across positions 3 and 5 (Third approach) as well as positions across 5 and 6 (Fourth approach). Therefore, the simulated bump resistance was 0.77, 0.83, and 0.83 mΩ for the first, third and fourth approaches, respectively. Similarly, the theoretical bump resistance for second approach can be obtained by simulation, and the value was 0.76 mΩ. Table 4-2 summaries the experimental and simulation results on bump resistances for the four

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approaches. The measured bump resistance was 0.89, 0.87, 0.96, and 0.94 mΩ, whereas the simulated value was 0.77, 0.76, 0.83, and 0.83 mΩ for the four approaches respectively. The experimental results were approximately 12-14 % higher than the simulated values. The difference may be attributed to the variation in bump height, and the temperature differences between the simulation and the measurement. In the simulation, the resistivity values adopted was at 20 °C, but the measurement was done at temperature range 25-30 °C. Although the experimental values were higher than the simulated ones, geometrical effect shows the same trend for both results. Therefore, the simulation results are in good agreement with the experimental data. These results indicate that serious current crowding effect occurs in the flip-chip solder joints.

On the basis of the simulation results, the real bump resistance should be equal to voltage difference between the current entrance point and the leaving points divided by the current. In the case of first approach as shown in Figures 4-11, the real bump resistance should be 7.7 mΩ. However, the measured bump resistances for the four approaches were less than 0.9 mΩ. The low measured values for bump resistance may be attributed to the serious crowding effect in the solder joints. Our previous 3D simulation shows that the current did not spread uniformly in the UBM opening.

Instead, the current crowded into the solder bump in a small volume near the entrance

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point of Al trace [16]. Little amount of the current passed through the opposite end of the entrance point of the current. Therefore, the voltage drops measured by the first approaches were much lower. For the third and fourth approaches, Kelvin probes for measuring voltage drops were closer to the current crowding region than those in the first and second approaches. Consequently, the measured values by the third and fourth approaches were larger than those by the first and second approaches.

Three components, Al pad (disc), UBM/solder, and Cu pad (disc), as shown in Figures 4-12 (a) to (c) may contribute to the bump resistance. From the simulation results, the bump resistance was 7.7 mΩ. In this paper, we denoted the bump resistance as the voltage drop across positions 1 and 2 which divided by the applied current. Therefore, the bump resistance included the above three components. Among them, Al disc contributed to the bump resistance most. This is because the cross-section of Al disc was quite small, approximately 1.5 μm × 100 μm. The current needs to flow through part of Al disc adjacent to Al trace in order to enter the solder joints through passivation opening, as shown in Figure 4-12 (a). The resistance of the partial Al disc was estimated to be 5.5 mΩ, which was about 72% of the bump resistance. In addition, since the cross sections for UBM/solder and part of the Cu disc was much larger than that of Al disc, they contributed only the rest of 21% resistance.

This bump resistance of 7.7 mΩ was larger than expected. We assume that the

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current flows through the joint uniformly as illustrated schematically in Figure 4-13 (a). The resistance based on this assumption was estimated to be only 1.0 mΩ for our solder joints. In fact, the current path was not uniform, as depicted schematically in Figure 4-13 (b). The current entered the solder joints from Al trace, drifting in the left-hand side of Al disc, crowding into the solder joints from the passivation opening, spreading out gradually as well as drifting toward the substrate side, and leaving the joint from Cu disc. Due to this current path, the bump resistance was about 7.7 times larger than that for uniformly distributed current.

Thermal-electrical effect might affect the measurement of bump resistance.

When two materials are joined together and a temperature difference ΔT is applied between two junctions, an open circuit voltage ΔV is established in the circuit when electric current I approaches zero. The Seebeck coefficient, α, is defined as [76, 77]:

=0

Therefore, if there is a temperature difference across the solder bump, there would be a voltage drop there. To estimate the magnitude of the voltage drop due to thermal-electrical effect in this measurement, we assumed the temperature difference across the solder bump is 1 °C, which is reasonable since the Joule heating effect in this study was less than 1 °C. The Seebeck coefficients at 300 K for Al, Cu and Sn are -1.66, 1.83, and -1 μV/K. Therefore, the voltage drop due to thermal-electrical effect

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is approximately 1.5 μV, which is about 1~2 % of the voltage drop in the solder bump when applied 0.2 A. As a result, the influence of thermal-electric effect could be neglected in this study.

Based on the above results and discussion, a layout for Kelvin structure is proposed to measure the bump resistance, as shown in Figure 4-14. It is denoted as approach 5 in this paper. One voltage terminal is connected near the entrance of Al trace, and the other voltage terminal could be at any position on the substrate side, since the voltage at the substrate was almost constant. However, the measured value is the combination of part of Al trace and the bump resistance. The bump resistance can be obtained by excluding the resistance of Al trace. When the terminal is very close to the bump, the measured value will be near the bump resistance. Gee et al. has used this structure to monitor the bump resistance changes during electromigration [73].

The resistance they measured was as high as 26 mΩ. This high value may be mainly attributed to the larger bump height of about 250 μm, and to the resistance comprised part of the resistance of Al trace.

Although the bump resistance may not be a critical issue for signal delay consideration, it has been used to monitor the resistance change due to void formation during reliability test [77,78]. Zhang and Baldwin fabricated the Kelvin bump structure to monitor the bump resistance changes during power cycling, and the

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resistance they measured were about 2 to 4 mΩ at room temperature for eutectic solder bumps with 125 μm in diameter [78]. Amagai et al. defined the failure of the solder joints during drop test by an increase in bump resistance by 1.2 times [79]. To examine the resistance change due to void formation, a void was inserted in the simulation model, as shown in Figure 4-15. The void depleted approximately 18% of the UBM opening. As the void formed near the entrance of the left Al trace, more current was forced to drift farther in the Al pad and entered the right-hand side of the solder bump, causing the increase in the bump resistance. The resistance increases due to the void formation measured by the four approaches are listed in Table 4-3. It was found the resistance increase was only 0.12 mΩ, which is approximately 15%

increase in bump resistance. However, if the Approach 5 in Figure 8 is adopted to monitor the bump resistance, the change was only 6.5%. Therefore, the approaches 1 through 4 are more sensitive to void formation.

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Figure 4-9: (a) Plan-view schematic of the layout design. Al trace connected all the four solder bumps together. Six nodes in the substrate side are labeled.

Cross-sectional diagram shows the experimental setup for (b) Approach 1. (c) Approach 2. (d) Approach 3. (e) Approach 4.

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Figure 4-10: The measured bump resistance as a function of temperature up to 150 °C for the four approaches.

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Figure 4-11: (a) Simulation results shows the current density distribution across the solder joints upon applying by 0.2 A. (b) The voltage distribution in the solder joints.

Voltage drop mainly occurred in Al trace. (c) Cross-sectional view along the YZ plane in (b) shows that voltage drop inside the solder bump mainly occurred at the high current density region. (d) Voltage distribution in the solder joint, excluding Al trace and Cu line. Six positions were labeled for measuring the voltage drop.

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Figure 4-12: Three components contributing to the bump resistance, includ (a) Al disc, (b) UBM/solder, (c) Cu disc. The resistance of Al disc contributed about 79% of the total bump resistance.

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Figure 4-13: Schematic drawings shows (a) the uniform current distribution and (b) the current crowding effect in the solder joints.

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Figure 4-14: Proposed layout of Kelvin structure for measuring bump resistance of the flip-chip solder joint.

Figure 4-15: The voltage distribution in the solder bump when a void depleted approximately 18% of the UBM opening.

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Table 4-1: The simulation voltages at the six positions in Figure 4-11 (b).

Positions for voltage measurement

1 2 3 4 5 6

Voltage (mV) 1.66 0.12 0.36 0.17 0.16 0.17

Table 4-2: Experimental and simulation results on bump resistances for the four

approaches.

Approach

Node 1 2 3 4

Experimental (mΩ) 0.89 0.87 0.96 0.94

Simulation (mΩ) 0.77 0.76 0.83 0.83

Table 4-3: The resistance increases due to the void formation measured by the different approaches in this study.

Approach 1 2 3 4 5

Ro (mΩ) 0.77 0.76 0.83 0.83 7.7

R1 (mΩ) 0.89 0.88 0.95 0.95 8.2

(R1- Ro)/Ro (%) 15.6 15.7 14.5 14.5 6.5

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4.3.2 Summary

Kelvin structures for flip-chip solder joints were designed and fabricated to measure bump resistance. The measured bump resistance strongly depended on the layout of the Kelvin bump structures. The simulation results indicated that the difference in bump resistance could be as large as 9 times when the voltage drop was measured at different positions. It was found that the serious crowding effect may be responsible for the significant geometrical effect of bump resistance in flip-chip solder joints. The simulation results indicated that the approaches 1 through 4 are quite sensitive to detect the void formation, and thus they are quite suitable for monitoring the resistance change due to void formation.

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