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Design of Bi-Phase Stimulus Driver to Suppress Epileptic Seizure with Current-Mode Adaptive

Loading Consideration

4.1 Introduction

With the consideration of reliability and power consumption, the stimulus driver used in the implantable device for epileptic seizures control is investigated in this work. The required stimulus current ranges from 20 μA to 50 μA in cooperative experiment. The effective impedance of electrode varies from 25 kΩ to 200 kΩ because of different kind of tissue, location, and implanted time. In order to meet the requirements, output voltage range of stimulator should be designed from 0.5 V to 10 V, that higher than operating voltage in common used. Therefore, the 0.35-μm 3.3-V/24-V BCD process is utilized in this work for the stimulus driver and chip implementation. Power consumption is also the critical consideration, because it is inversely proportional to the use time in implantable device. In order to minimize power consumption of this stimulator, supply voltage of this work can be adjusted according to different impedance by current-mode adaptor.

To integrate with implantable epileptic seizure monitoring and controlling system, the high operating voltage for 24-V device should been generated by stimulus driver itself while rest of the system utilize the same operating voltage (VDD). Therefore, charge pump circuit is an indispensible part of the stimulus driver. This work, charge pump has been integrated into this proposed stimulus driver. In addition, as common

applications of electrical stimulation, bi-phase stimulus current are recommended for stimulating [2], [35]. This proposed stimulus driver delivers bi-phase stimulus current by two leads electrode per stimulus site with single supply voltage. The bi-phase stimulus current is generated by altering the current path by changing switches. The detailed circuit simulation and measurement results of the proposed design will be presented in the following sections.

4.2 Novel Bi-Phase Stimulus Driver with Current-Mode Adaptive Loading Consideration

Electrical stimulation therapies are new generations of medical science. A number of diseases that lack of properly treatment in the past are curable by functional electrical stimulation (FES) or therapeuticelectrical stimulation (TES). Thus, stimulus drivers for medical treatment become a prospective research topic currently, and a variety of design of stimulus driver have been researched and pronounced; according to these researches and applications, the mainly considerations of stimulus driver for medical treatment have been investigated too.

Power consumption is one of mainly consideration of stimulus driver in any applications. To minimize power consumption of stimulus driver while tissue impedance varies in a wide range which causes required operating voltage of output stage changes largely, in this chapter, stimulus driver with current-mode adaptor is investigated.

In addition, the proposed stimulus driver is a sub-circuit of whole system, each sub-circuit of the system should adopts identical power supply voltage (VDD). Thus, the high operating voltage for 24-V device of stimulus driver should be generated by stimulus driver itself, charge pump circuit is integrated into proposed stimulus driver.

4.2.1 Design of Charge Pump Circuit

Charge pump circuits have been used to generate dc voltages those higher than the power supply voltage (VDD) or lower than the ground voltage (GND). In this work, out-of-phase. When the clock signals of the first and the third pumping stages in path A are Clk, those in the path B are Clkb. Likewise, when the clock signals of the second and the forth pumping stages in the path A are Clkb, those in the path B are Clk. Thus, paths A and B can see as two independent charge pump circuits but with the same output node. Due to clock signals of path A and path are out-of-phase, the voltage waveforms of nodes 1-4 and node 5-8 are interweaved. The detailed operation of charge pump circuit is shown below.

In first pumping stage, as shown in Fig. 4.1(a), the clock signal Clk is low and the clock signal Clkb is high during the time interval T1. At the moment, the voltage difference (V15) between node 1 and node 5 is –VDD. Thus, transistor Mn1 is switched on to deliver the charges from the power supply (VDD) to node 1, but the transistor

Mn5 is switched off to cut off the path from node 5 back to the power supply. That is to say, V15 is VDD during the time T2. Transistor Mn1 is switched off to cut off the path from node 1 to the power supply, but the transistor Mn5 is switched off to deliver the charge from the power supply to node 5.

In the second stage, when the clock signal Clk is low and the clock signal Clkb is high during the time interval T1, V15 and the voltage difference (V26) between node 2 and node 6 are –VDD and VDD, respectively. Therefore, transistors Mp5 and Mp6 are switched on to transfer the charges from node 5 to node 6, but transistors Mp1 and Mn2 are switched off to cut off the path from node 2 back to node 1. Namely, V15 and V26 are VDD and –VDD during the time interval T2, respectively. Transistors Mp5 and Mp6 are switched off to cut off the path from node 6 back to node 5, but transistors Mp1 and Mn2 are switched on to deliver the charges from node1 to node 2. The operation of third stage is similar to the second stage.

The output stage of path A and path B are jointed. When the clock signal Clk is low and the clock signal Clkb is high during the time interval T1, the voltage difference (V48) between node 4 and node 8 is VDD. Thus, transistor Mp4 is switched on to transfer the charge from node 4 to the output, but transistor Mp8 is switched off to cut off the path from the output node back to node 8. Besides, V48 is –VDD during the time interval T2. Hence, the transistor Mp4 is switched off and the current path from the output node back to node 4 is cut off. In addition, the transistor Mp8 is switched on to transfer the charges from node 8 to the output node. Ideally, the output voltage of the charge pump circuit with 3.3-V power supply voltage (VDD) should be as high as 16.5 V. However, due to the parasitic capacitance at each pumping node and the loading of the output current of 100 uA, the simulated output voltage of the charge pump circuit is 14.56 V. The device dimensions of the charge pump circuit are shown in Table 4.1.

(a)

Fig. 4.1. (a) Charge pump circuit and (b) corresponding waveforms of the charge pump with four pumping stages [39].

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