Device Analysis

In order to quantify the benefit in strain engineering by using SASR, we implemented the e-SiGe profiles of the control and SASR samples into a well calibrated TCAD simulator. The simulation results of mechanical strain are displayed in Fig. 4.4 which reveals the key advantage of SASR in strain engineering. The tip of the e-SiGe was modulated from sub-surface to the silicon surface. This led to a much closer e-SiGe surface proximity as compared to the control sample. According to the simulation results, the SASR sample exhibits a highly localized strain inside the channel region around the gate edge which is most efficient to enhance the carrier mobility.

On the contrary, the control sample shows a highest strain outside the channel region and therefore a lower strain efficiency is evident as compared to the SASR sample. Without modifying the following e-SiGe epitaxy composition, the longitudinal compressive strain in the channel region of the SASR sample is increased by a factor of more than 15% and thereby a higher hole carrier mobility is expected as compared to the control sample.

In addition to the benefit resulting from higher strain efficiency, the hole carrier mobility and boron doping activation level are higher in SiGe as compared to those in silicon. Therefore, SASR can lower the Rsd as long as the e-SiGe stays at the gate edge. Here, a 14% difference in Rsd is obtained (as shown in Fig. 4.5) in terms of the statistical distributions in samples with and

without SASR. It is noted that the Rsd values are measured using the extraction method described in the previous work [6.17], [6.18]. The figure also clearly points out the fact that a tighter distribution of Rsd is associated with SASR. This implies that SASR can mitigate the process variation caused by the silicon-recess etching process.

Unlike the conventional proximity-push by using merely etching process which may potentially lead to undesirable short-channel-effect (SCE), SASR can actually alleviate the undesirable SCE because of a less encroachment of e-SiGe in the sub-surface region as depicted in Fig. 4.3(b). This was experimentally confirmed by the measured threshold voltage versus gate length (Vth vs. Lgate) characteristics as given in Fig. 4.6. The figure indicates that a higher degree of SCE suppression is achieved with the implementation of SASR. One should note that there is no other process difference between these two samples. The improvement in the SCE characteristics should purely result from SASR-induced e-SiGe profile change. Because of a higher Vth level in the short channel region by using SASR, we should have room to reduce the halo ion-implantation dose in order to further boost the device performance.

Fig. 4.7 compares and shows the measured Ion-Ioff performance between the samples with and without using SASR. Evidently, a more than 10%

improvement is obtained with SASR, which certainly can be attributed to the combinational effects of the higher hole carrier mobility and lower Rsd as mentioned above. The variation in the Ion-Ioff performance is also significantly reduced in the presence of SASR. Both the tightened distributions of Rsd and Ion-Ioff performance reflect the advantage of this self-aligned process (SASR)

over the conventional approaches.

4.4 Conclusion

An integration-friendly and cost-effective process used for strain engineering, SASR, is at the first time highlighted in this chapter. Owing to the nature of self-aligned silicon-reflow in the hydrogen ambient, extreme surface proximity-push is achieved without using sophisticated etching process. SASR is proven stable in a wide range of process temperature, which is highly desired in the advanced CMOS manufacturing.

Significantly improved Ion-Ioff performance is experimentally demonstrated by implementing SASR on a 40nm technology pMOSFET, resulting from the combinational effects of the higher hole carrier mobility and lower Rsd. The statistical distributions of Rsd and Ion-Ioff performance are tightened up for the reason that the e-SiGe proximity-push is realized in a self-aligned manner. Improved drain-induced-barrier-lowering (DIBL) is also obtained because of a less e-SiGe encroachment in the bottom region. These analyses are supported by TEM photos and corroborated by TCAD simulation. Our study may provide an alternative approach to the extreme e-SiGe surface proximity for the current and coming VLSI generations.

Fig. 4.1 Cross-generation drive current (drain current measured at Vg=Vd=1V) comparison [4.13]. The gap between NMOS and PMOS decreased constantly from 90nm to 32nm technology.

The strain and Rsd engineering of e-SiGe played an important role in the PMOSFET performance enhancement.

Fig. 4.2 A brief process flow in the e-SiGe formation loop. An optional hydrogen annealing step is inserted before e-SiGe selective epitaxy process.

Fig. 4.3(a) Cross-sectional TEM analyses of e-SiGe profile under different hydrogen annealing temperatures. Complete and self-aligned silicon-reflow occurs above a moderate temperature which is 800°C in this work. Wide process window of annealing temperature is demonstrated. The hydrogen annealing time is 1minute for each process.

Fig. 4.3(b) A comparison of e-SiGe contour between the control sample and SASR. SASR provides a closer proximity at the top and less e-SiGe encroachment at the middle and bottom regions.

(b)

No reflow 750℃ , 1 min 800℃ , 1 min 850℃ , 1 min

Partial reflow Complete reflow, SASR Complete reflow, SASR

No reflow

Without

No reflow, Control sample

(a)

No reflow

Insufficient reflow

Anneal condition:

Fig. 4.4 A two-dimensional TCAD simulation of stress distribution along the channel direction. SASR provides higher compressive stress which improves hole carrier mobility.

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