Results and Discussion

Fig. 3.2 shows the TEM cross-section of both the NMOSFET and PMOSFET under a series of silicide phase transformation conditions (silicidation-RTA2 using MSA). It is evident that a process window of MSA conditions exists in terms of forming FUSI gate on the P⁺ poly-silicon gate while the N⁺ poly-silicon gate keeps non-FUSI. Because of the heavy incorporation of nitrogen impurity of more than 10¹⁵ cm^-2 ion implantation

dose in the N⁺ poly-silicon gate, silicidation rate is significantly retarded. The retardation of silicidation rate caused by nitrogen was also observed in [3.4].

Consequently, selective P⁺ FUSI gate can be formed by modulating the MSA thermal budget and the nitrogen concentration in the N⁺ poly-silicon gate.

The silicide phase of the P⁺ FUSI gate, confirmed by analyzing the electron diffraction pattern, is NiSi2 as also depicted in Fig. 3.2.

(a) On the Device Performance

As shown in Fig. 3.3 and Fig. 3.4, both the threshold voltage (Vth) shift of long channel PMOSFET and flat band voltage (VFB) shift of the PMOSFET CV curve clearly demonstrate a workfunction (WF) shift of ~150mV. Therefore, this P⁺ FUSI gate has a WF about 150mV above the valence band edge and it still behaves likes a p-metal. The original P⁺ poly silicon gate was heavily doped with boron dopant during the P⁺ S/D ion implantation with a dose >

3x10¹⁵ cm^-2. It is confirmed that the heavily boron-doped FUSI can be used as a p-metal [3.5-3.10]. Because of a limited WF shift, the adjustment of doping profile toward a reasonable Vth level is not difficult. In order to provide a similar Vth level for short channel devices, a lower halo ion implantation dose was utilized to compensate for the 150mV WF-shift. As a result, similar PMOSFET Vth level was achieved in the short channel MOSFETs. Smooth PMOSFET Vth roll-off behavior also indicates a single-phase P⁺ FUSI gates for gate length ranging from 10m to 30nm. As shown in Fig. 3.5, a tight PMOSFET Vth distribution guarantees a single-phase and uniform P⁺ FUSI gate formation.

As to the NMOSFET, using a moderate MSA condition provides little Vth

difference compared to the conventional soak-annealing for all gate lengths as exhibited in the upper part of Fig. 3.3. As shown in Fig. 3.5, a tight NMOSFET Vth distribution indicates that all of the N⁺ poly-silicon gates remained non-FUSI. It is evident that this MSA-assisted FUSI gate formation process shows no dependency on gate length for both NMOSFETs and PMOSFETs.

This is a noticeable advantage on the process simplicity over the conventional methods which may need extra mask layers, partial poly gate recess processes, and separate nickel supply for long channel and short channel devices.

NMOSFET showed an unchanged relation of the inversion state gate oxide thickness and the inversion state gate current (Tox_inv vs. Jg) while PMOSFET clearly demonstrated a 0.3nm thinner Tox_inv as indicated in Fig. 3.6.

This is the evidence of the elimination in PMOSFET poly-depletion-effect with P⁺ FUSI gate formation.

Fig. 3.7 shows the difference in device Ion-Ioff performance between non-FUSI and FUSI gates. NMOSFET shows an obvious degradation when N⁺ FUSI gates are formed under a non-optimal MSA condition. This implies that the “memorized” strain resulting from SMT may be relaxed because of the consumption of strained N⁺ poly-silicon gate. This result is consistent with what has been proposed in [3.4] showing poor compatibility between N⁺ FUSI gate and the performance enhancement resulting from SMT for NMOSFETs.

In order to prevent this NMOSFET Ion-Ioff degradation, we optimized the MSA-assisted silicidation process for FUSI gate formation exclusively on P⁺ poly-silicon gate while preventing FUSI gate formation on N⁺ poly-silicon

gate. The NMOSFET Ion-Ioff degradation was thereby prevented, while the FUSI-gated PMOSFET devices showed an enhancement in Ion-Ioff performance of more than 20%. It is believed that this PMOSFET enhancement can be attributed to at least three factors. 1^st: the reduced halo ion implantation dose which reduced impurity scattering. 2^nd: the thinner Tox_inv resulting from elimination of poly-gate-depletion. 3^rd: the change in mechanical stress induced by the FUSI gate. Based on the measurement data shown in Fig. 3.8, the stress level of MSA-assisted FUSI gate is ~500MPa more tensile than the stress level of the poly-silicon gate after silicidation. Hence, a FUSI gate may impose a stronger compressive stress on the underlying PMOSFET channel region. This fact was verified by using TCAD simulation as shown in Fig. 3.9 by implementing the measured stress level in the gate region into a well calibrated device simulator [3.13]. It is clear that FUSI-gated device shows a

~460MPa higher compressive strain in the middle of channel region as compared to the poly-silicon gated device. The hole carrier mobility is thereby enhanced.

(b) On the Silicide Morphology and Junction Leakage Performance

In this work, the MSA-assisted silicidation process also improved the nickel silicide formation quality. Compared to the conventional RTA2 process using soak-annealing, a smoother silicide/silicon interface was obtained by replacing soak-annealing with MSA as shown in Fig. 3.10. Consequently, MSA-assisted silicidation process can potentially improve the junction leakage resulting from random silicide spiking. Fig. 3.11 compares the SRAM junction leakage behavior between soak-annealing and MSA-assisted

silicidation. Compared to the soak-annealing process, a tighter junction leakage distribution was observed in the N⁺ diffusion/P_Well junction structure by using MSA-assisted silicidation while an unchanged P⁺ diffusion/N_Well leakage behavior was obtained. In terms of junction leakage control, MSA-assisted silicidation outperforms the conventional soak-annealing process.

Fig. 3.12(a) compares the sheet resistance distributions for narrow silicided N⁺ and P⁺ diffusion regions between two poly-silicon lines. This is often the most sensitive test-pattern than tells the quality of silicide formation.

Equally tight distributions were achieved between RTA2 using soak-anneal and RTA2 using MSA. The values of the sheet resistance are the same in these two processes, indicating the same silicide phase in the diffusion regions. The sheet resistance distributions for 30nm-wide silicided poly-silicon lines are shown in Fig. 3.12(b). RTA2 using MSA led to a remarkably higher sheet resistance of the silicided P⁺ poly-silicon lines due to the FUSI gate formation in a different phase of nickel silicide (NiSi2) while the sheet resistances of the silicided N⁺ poly-silicon lines were not significantly changed. No matter for N⁺ or P⁺ poly-silicon lines, MSA-assisted silicidation provides tight distributions for the narrow silicided poly-silicon lines.

3.4 Conclusion

An MSA-assisted silicidation process is proposed in this work. By using optimum MSA conditions for the silicide phase transformation, single-phase (NiSi2) FUSI gates can be uniformly and exclusively formed for PMOSFETs in various device dimensions while preserving a FUSI-free N⁺ Poly-silicon gate

with feature size down to 30nm. There is definitely a process window for the MSA-assisted silicidation process to simultaneously form FUSI gates and thin silicided diffusion regions without using additional CMP, lithography layers and poly-silicon etch-back processes.

An enhancement in PMOSFET Ion-Ioff performance of more than 20% is experimentally realized because of the elimination of poly-depletion-effect and the FUSI-gate-induced compressive channel strain. Considering the significant improvement in device performance and the unique integration-friendly features, this MSA-assisted FUSI gate formation is very promising for the current and coming VLSI generations.

Fig. 3.1 Process steps in the vicinity of silicidation process. Either a soak-annealing or an MSA is utilized for RTA2 for silicide phase transformation.

Non-reacted Nickel removal