Device Fabrication Process

In this experiment, typical top-gate, coplanar self-aligned poly-Si TFTs were fabricated on the glass substrates and crystallized by ELA method. The Poly-Si TFTs with and without LDD structure were also fabricated, respectively. The schematic cross-sectional view of the devices is shown in Fig.2-1 and Fig.2-2 in page 7. The device manufacturing process is described below and shown in Fig.2-3 in page 8.

First, the oxide buffer layer was deposited on the glass substrate to prevent the diffusion of the impurities existing in the glass substrate from the silicon layer. Then, the undoped 50-nm-thick a-Si layer was deposited on the buffer layer. After that, the a-Si films were recrystallized by ELA method with 420mJ / cm²laser energy, and the recrystallized poly-Si films were patterned into the active islands. Afterward, the gate insulator layer was deposited. Here the gate insulator layer was combined with the 50-nm-thick silicon oxide layer and the 20-nm-thick silicon nitride layer. Next, phosphorus ions were implanted to form the n^＋ source/drain regions and the n^－LDD regions. However, the TFTs without LDD would skip the step which was implantation of n^－LDD regions. These dopants were activated by thermal process.

Finally, metal layer was deposited and then patterned for the source/drain and gate regions as the metal pads. The brief specification of the devices is show in Table I.

Fig.2-1 The schematic cross-sectional view of the W/L = 6μm / 6μm N-type Poly-Si TFT with LDD structure

Fig.2-2 The schematic cross-sectional view of the W/L = 6μm / 6μm N-type Poly-Si TFT without LDD structure

Fig.2-3 The fabrication process of the W/L = 6μm / 6μm N-type-Si TFTs.

2.2 Simulation Method

2.2.1 Definition of the LDD Channel Extension

In our experiment, HP4156 was applied to measure the current-gate voltage (ID-VG) in order to extract the LDD resistances. Then plotted the comparison between the LDD resistance and LDD length diagram, and calculated the intercept of x axis as the experimental data of extended channel, which is shown in Fig.2-4 in page 9.

The simulation software, Silvaco, was used to simulate the current density distribution of the devices during on-state and extract the surface current density from the interface which was between gate and insulator. Those are shown in Fig.2-5 and

Source

Fig.2-6 in page 10. When the surface current density decayed from the maximum to e^-1 times, we defined this distance between the edge of the gate electrode as channel extension length, which is shown in Fig.2-7 in page11.

Fig.2-4 The definition of LDD channel extension length which is extracted from the W/L = 6μm / 6μm N-type-Si TFTs.

ΔL

Fig.2-5 The current density distribution of TFT with 1μm LDD under VGS = 15V.

Fig.2-6 The surface current density distribution of TFT with 1μm LDD under VGS

which are 3, 9, and 15V.

Lateral Position (μm)

Vertical Position (μm)

LDD n⁺

Lateral Position (μm) Current Dens ity ( A/cm

2

)

LDD = 1μm

Channel_Gate LDD n⁺

Fig.2-7 The definition of LDD channel extension length which is extracted from the simulation result.

2.2.2 Simulation Method

According to the above definition of the LDD channel extension, we compared the experimental data with simulation results under various gate biases and temperatures to determine the defects of poly-Si film. The compared results are shown in Fig.2-8 and Fig.2-9. The trap density of states (DOS) is shown in Fig.2-10.

In the DOS figure, where

NGA：The total density of acceptor-like states in a Gaussian distribution, and unit is cm^-3.

NTA：The density of acceptor-like states in the tail distribution at the conduction band edge, and unit is cm^-3/eV.

Lateral Position (μm) Current Density ( A/cm2 )

△L

e

^-1

Gate LDD n⁺

N_TA= 1.12x10²⁰ cm^-3/eV N_GA= 6x10¹⁷cm^-3

Temperature ( K )

220 240 260 280 300 320 340 360 380

Δ L ( μm ) Simulation V_GS= 3V Raw Data V_GS= 9V Simulation V_GS= 9V Raw Data V_GS= 15V Simulation V_GS= 15V

V_GS = 15V

9V

3V

Fig.2-8 The comparison between the raw data and simulation result under various gate biases.

Fig.2-9 The comparison between the raw data and simulation result under various temperatures.

Fig.2-10 The initial trap density of states (DOS) which is matched with the real device.

Then, the simulation would be divided into two major parts. One part was discussion about the effects of gate insulator thickness, LDD length, bias voltage, temperature and poly-Si thin film property on LDD channel extension. The other part, we researched the relation of two kinds of structures, the typical and gate overlapped LDD (GOLD) TFTs’ structures, between electric filed and LDD doping concentration during off-state.

The total simulation various parameters of every section are show in Table II to Table VI.

N_GA=6×10¹⁷cm^-3 N_TA=1.12×10²⁰cm^-3/eV

Density of States ( cm-3/eV )

Chapter 3

Results and Discussions

3.1 The Influence Factors on LDD Channel Extension

3.1.1 Gate Insulator Thickness and Bias Voltage

First, base on the simulation parameters which are determined in chapter 2, we change the gate biases from 3 to 15V and gate insulator thicknesses from 60nm to 150nm. The comparison diagram between LDD channel extension length (ΔL) and gate biases with respect to different gate insulator thicknesses is shown in Fig3-1.

Fig.3-1 The influence of gate insulator thickness on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table II.

N_TA = 1.12x10²⁰ cm^-3/eV

Obviously, ΔL and gate biases are positive correlations. However, ΔL and gate insulator thicknesses are negative correlations. The major simulation parameters are shown in Table II.

While the gate bias is arisen, the y-direction vertical electric field between gate and drain is increased. Consequently, the additional gate induced carriers’ region which can regard as the extended channel length is also increased. On account of the same reason, adding the gate insulator thickness causes the vertical electric field is abated and ΔL is decreased.

Second, fix the gate insulator thickness in the initial condition which is 60nm.

Change the gate biases from 3 to 15V and change the LDD doping concentration from 1.2×10¹⁸ cm^-3 to 1.2×10¹⁹ cm^-3. We can observe that increasing doping concentration causes that ΔL is curtailed, which is shown in Fig3-2.

The influence of gate biases that can affect the vertical electric field has been described previously. Increasing LDD doping concentration can directly reduce the energy barrier height of the grain boundary, and diminish the resistivity of LDD.

Therefore, the carriers in the LDD region can overcome the grain boundary barrier and move more easily toward the drain electrode in the horizontal direction. Because of more difficult to keep the carriers in the LDD region near the gate electrode, we will see the ΔL seems to be suppressed.

Fig.3-2 The influence of LDD doping concentration on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table II.

3.1.2 LDD Length

Following the previous simulation manner, the variable which is insulator thickness is replaced by LDD length. And TFTs’ LDD lengths change from 0.5μm, to 2μm in Fig.3-3. The major simulation parameters are shown in Table III. As the LDD length is increased, ΔL only increases linearly in the initial regions and achieves respectively saturation values in the longer LDD length regions.

Over the 1μm LDD, the ΔL is saturated. The saturation values are directly equal to the result of 60nm in Fig.3-1 in section 3.1.2. But as LDD less then 1μm, ΔL is limited by the length of LDD region. According to these two trends, the influence of

N_TA = 1.12x10²⁰ cm^-3/eV

LDD Concentration = 1.2x10¹⁸ cm^-3

2.00x10¹⁸

2.54x10¹⁸

4.00x10¹⁸

1.20x10¹⁹

Fig.3-3 The influence of LDD length on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table III.

the gate voltage can be deduced that the gate bias may only control a limited region around the gate electrode. The effect of different LDD length on ΔL is limited only while the gate voltage is large enough to induce ΔL which is longer then LDD length.

Briefly, while the influence of gate bias is large than the length of LDD, the ΔL is limited as the length of LDD, on the contrary, the ΔL will be equal to the result of 60nm in Fig.3-1.

3.1.3 Temperature

When applying the poly-Si TFTs in the circuits, the temperature is also a significant problem. Hence, we vary the LDD doping concentration with the different

N_TA = 1.12x10²⁰ cm^-3/eV

surrounding temperatures which are 233K, 298K, and 363K. The simulation result is showing in Fig.3-4. The major simulation parameters are shown in Table IV. We can observe that when the temperature is increased, ΔL is decreased.

Fig.3-4 The influence of temperature on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table IV.

In this figure, there are two factors to affect ΔL. The influence of doping concentration has been described in previous 3.1.1 section. The other factor, temperature, will determine the thermal velocity of the carriers. Hence, the carriers are able to own higher thermal energy and thermal velocity when we increase the temperature. The carriers have higher thermal velocity. It means that the carriers spend less time stopping around the dopants and suffer less impurity scattering. The

NTA= 1.12x1020

carriers have higher thermal energy. In other word, more carriers can overcome the grain boundary barrier. So the carriers can move to drain electrode more quickly and possibly. At the same time, the gate bias will be hardly to keep the carriers. Base on above reasons, ΔL is dominated by thermionic emission effect and impurity scattering effect in temperature response. Hence, we can observe this phenomenon, increasing the surrounding temperature reduces the ΔL.

3.1.4 The Poly-Si Thin Film Property

After discussing about the basic factors, in this section, we will focus on the poly-Si thin film properties in detail. Because this is a n-type TFT, in the density of states (DOS) of the thin film, the main influence on induced carriers’ numbers is acceptor-like state region which is composed by two states which are acceptor-like deep state and acceptor-like tail state. In the Slivaco software, the deep state is assumption as a Gaussian distribution and the tail state is assumption as an exponential distribution. There are two parameters can adjust these two states. One is NGA which specifies the total density of acceptor-like states in a Gaussian distribution, and unit is cm^-3. The other is NTA which specifies the density of acceptor-like states in the tail distribution at the conduction band edge, and unit is cm^-3/eV. Therefore, we can through varying the NGA and NTA to respectively adjust the deep state and tail

state in the acceptor-like state of the DOS.

First of all, we fix the NGA which is 6×10¹⁷ cm^-3, and modify the NTA as 1.12×10¹⁷, 1.12×10¹⁸, and 1.12×10¹⁹ cm^-3/eV. The major simulation parameters are shown in Table V. The DOS is shown in Fig.3-5. Again, we change the LDD doping concentration with above three kinds of the DOS to analysis the influence on ΔL, which is shown in Fig.3-6. However, except the effect of doping concentration, the various NTA values seem to only make little variations.

Then, the NTA and NGA exchange for each other. In this time, we fix the NTA

which is 1.12×10²⁰ cm^-3/eV, and modify the NGA as 1×10¹⁷, 3×10¹⁷, 6×10¹⁷ and 1.2×10¹⁸ cm^-3. The major simulation parameters are shown in Table V. The simulation result is shown in Fig.3-7. The DOS is shown in Fig.3-8. Although the NGA are different, the effects of doping concentration are all the same： As increasing the doping concentration, ΔL will be decreased. While exceeding the turning points , ΔL will drop swiftly. Nevertheless, four kinds of NGA values have four respective critical points. In other words, the critical point and NGA have specific correlation.

According to the mechanism of ΔL explained in the preceding sections, we believe the extended current path from gate channel in LDD region is related to the resistivity of poly-Si thin film.

Fig.3-5 The density of states (DOS). NGA is fixed in 6x10¹⁷ cm^-3. (a) NTA=1.12x10¹⁹ cm^-3 , (b) NTA=1.12x10²⁰ cm^-3 , (c) NTA=1.12x10²¹ cm^-3

N_GA=6×10¹⁷cm^-3 N_TA=1.12×10²¹cm^-3/eV N_GA=6×10¹⁷cm^-3 N_TA=1.12×10²⁰cm^-3/eV N_GA=6×10¹⁷cm^-3 N_TA=1.12×10¹⁹cm^-3/eV

( a )

( b )

( c )

Fig.3-6 The influence of thin film property NTA on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table V.

Fig.3-7 The influence of thin film property NGA on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table V.

V_GS= 15V

Fig.3-8 The density of states (DOS). NTA is fixed in 1.12x10²⁰ cm^-3. (a) NGA=1x10¹⁷ cm^-3, (b) NGA=3x10¹⁷ cm^-3, (c) NGA=6x10¹⁷ cm^-3 (d) NGA=1.2x10¹⁸ cm^-3.

The correlation between resistivity and doping concentration is referred in Seto’s model [17]. Consider the depletion of the grain of poly-Si thin film, the correlation curve is shown in Fig.3-9 which also has a specific turning point at

N_GA=3×10¹⁷cm^-3 N_TA=1.12×10²⁰cm^-3/eV

N_GA=6×10¹⁷cm^-3 N_TA=1.12×10²⁰cm^-3/eV

N_GA=1.2×10¹⁸cm^-3 N_TA=1.12×10²⁰cm^-3/eV

( a ) ( b )

( c ) ( d )

N_GA=1×10¹⁷cm^-3 N_TA=1.12×10²⁰cm^-3/eV

N = Q_t / L (1)

where N is the doping concentration and unit is cm^-3.

Qt is the deep level trap density of state and unit is cm^-2.

L is the average grain length of poly-Si thin film and unit is cm.

Fig.3-9 The correlation between resistivity and doping concentration. [17]

Compared to our study,

GA GA

t N

L L N L

N =Q = × = (2)

Therefore, when the LDD doping concentration (N) is equal to NGA, ΔL should be going to drop rapidly. This assumption is matched perfectly with our simulation results in Fig.3-7.

Now, because of the critical point N = NGA, the Fig.3-7 can be divided into two regions to discuss. The two regions are the left-hand side N < NGA, and the right-hand side N > NGA. We transfer the diagram from Fig.3-7 into Fig.3-10. Vary the NGA from 1×10¹⁷ cm^-3 to 1.2×10¹⁸ cm^-3 with respect to different doping concentrations (N) which are 1×10¹⁷, 1.2×10¹⁸, and 4×10¹⁸ cm^-3. In this figure, the bottom curve is N >

NGA, the top curve is N < NGA, and the central curve is cross the N = NGA point.

Fig.3-10 The influence of LDD doping concentration and NGA on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table V.

resistivity and ΔL is increased conspicuously. In brief, the better thin film quality has fewer defects and higher conductivity, therefore has shorter extended channel length.

While N < NGA, the minimum NGA has the best thin film quality and the smallest resistivity, however, it also has the maximum ΔL in our simulation. This result is contrary to our earlier inferences. Clearly, there have other mechanisms which we do not realize to involve in.

Finally, we will additionally study the effect of thin film property on different temperatures. The major simulation parameters are shown in Table VI. In the section 3.1.3, we have proposed that increasing the surrounding temperature reduces the ΔL.

In the different thin film properties, this phenomenon is also existence. The results are shown in Fig.3-11 and Fig.3-12. The slope means the various degree of ΔL with respect to different temperatures.

While we adjust the NGA, the slopes are corresponding changed but the changes do not exist specific trends. In spite of the influence of the NGA on slope does not exist consistency, the NTA has different effect on slope. As the NTA is arisen, the decay of ΔL is also raised. The slope is more negative. These results we deduce that the increasing NTA causes the free carriers which is induced by gate voltage become fewer, so the influence of temperature will be more conspicuously. But why the various NGA does not have the same trend, the reasons we are still researching, now.

Fig.3-11 The influence of temperature and NGA on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table VI. (a) VGS=3V (b) VGS=9V (c) VGS=15V

V_GS= 3V N_TA= 1.12x10²⁰

Temperature ( K )

220 240 260 280 300 320 340 360 380

Δ L ( μm )

220 240 260 280 300 320 340 360 380

Δ L ( μm )

220 240 260 280 300 320 340 360 380

Δ L ( μm )

Fig.3-12 The influence of temperature and NTA on the channel extension effect obtained from Silvaco ATLAS simulation with parameters listed in Table VI. (a) VGS=3V (b) VGS=9V (c) VGS=15V

V_GS= 15V N_GA= 6x10¹⁷

Temperature ( K )

220 240 260 280 300 320 340 360 380

Δ L ( μm )

220 240 260 280 300 320 340 360 380

Δ L ( μm )

220 240 260 280 300 320 340 360 380

Δ L ( μm )

3.2 Optimal LDD Design for Both ON and OFF State

In the section 3.1, we realize that if we want to restrain the LDD channel extension through device fabrication process, we should grow better thin film which exists fewer defects or dope more dopants into the LDD region. However, the quality of thin film is limited by manufacture equipments and technologies. On the contrary, the method of controlling the doping concentration is easier to achieve the goal, reduce the LDD channel extension.

Doping more dopants into the LDD region can reduce the current path extended from gate channel while the TFT is on state. Nevertheless, as the TFT is off state, because of doping more dopants, the parallel electric field between gate and drain electrodes will increase and cause the leakage current arises. This outcome is contradictory to the original LDD’s purpose which is to suppress the leakage current during off state.

Therefore, in this topic, we will research the optimal LDD design for both on and off states by the discussion about the relation between ΔL and the parallel electric field.

3.2.1 Various Poly-Si Thin Film Properties

The Fig.3-13 is the parallel electric field distribution with different LDD doping concentrations which are 1×10¹², 2×10¹³, and 4×10¹³ cm^-3. The gate bias voltage is constant in -10V. Because of the electric field direction is from drain to gate in the off state, the values are negative. We choose left-hand side maximum values and compare them with the Fig.3-6 and Fig.3-7 in Fig.3-14 and Fig.3-15.

Fig.3-13 The parallel electric field distribution of TFT with 1μm LDD under VGS = -10V.

Gate LDD n⁺

N_GA=6×10¹⁷cm^-3 N_TA=1.12×10²⁰cm^-3/eV

LDD = 1.7E16 LDD = 4.0E18 LDD = 8.0E18

Doping Concentration

Fig.3-14 The comparison between the extension channel length and electric field with respect to different NTA.

Fig.3-15 The comparison between the extension channel length and electric field with respect to different NGA.

LDD Concentration ( cm^-3 )

Through the Fig.3-14 and Fig.3-15, we can point out the optimal LDD design criterion for both on and off states. For example, in our device, the optimal LDD doping concentration is located on about 3×10¹⁸ cm^-3. It is clear that in the optimal doping concentration, the TFT devices have the shorter extended channel and the lower parallel electric field. We can through this comparison to get the balance between these two problems which are channel extension and leakage current at the same time.

3.2.2 GOLD Structure TFT

Furthermore, in the end of section 3.2, we are interested in the gate overlapped LDD (GOLD) TFTs’ structure which can effectively suppress the leakage current. The overlapped LDD length is 1μm, and none extra LDD structure over out the gate channel. The structure, net doping profile, current density distribution, surface current density distribution, and parallel electric field distribution are shown in Fig.3-16 to Fig.3-19. The gate bias is constant in 15V during on state, and in -10V during off state.

The overlapped LDD concentration is from 1×10¹⁷ to 1×10¹⁹ cm^-3. We can see that the surface current density will drop quickly in the GOLD region as the doping concentration is too large. It perhaps reduces the effective channel length and derogates the performance of the TFTs. The comparison between ΔL and the parallel

electric field, the result is shown in Fig.3-20. Obviously, ΔL in the GOLD structure is almost equal to zero. The GOLD TFTs is an excellent structure to suppress the leakage current and LDD channel extension.

Fig.3-16 The net doping profile of the GOLD structure.

Fig.3-16 The net doping profile of the GOLD structure.

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