Chaper 3. Top-gated Graphene Transistors Fabricated on Graphene Grown Directly on
3.2.1. Device Performances of Top-gated Graphene Transistors
According to the result obtained from the ALD-grown Al2O3 growth conditions on graphene, we have adopted recipe III to grow the dielectric layers for the top-gated graphene transistors.
3.3. Comparison of Graphene Transistors between Top- and Bottom- gated Structure
After the top-gated graphene transistor is successfully demonstrated, further
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Fig. 3-15. IDS-VGS curve of sample 05 (recipe V).
Fig. 3-16. IDS-VGS curve of sample 06 (recipe VI).
doi:10.6342/NTU201600721 Purpose: Investigate the influence of increasing reactant H2O.
Table 3-5. Purposes and parameters of recipe 05 and recipe 06.
Sample No. 01 02 03 04 05 06
Table 3-6. Comparison and summary of top-gated graphene transistors. (Forward Swing).
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investigation of top- and bottom-gated transistors are performed by fabricating dual-gate transistors and is discussed in this section. The dual-gated transistor is fabricated in a sequential process which provides four samples for investigation of different structures (Table 3-7).
The dual-gate transistors is fabricated by the following process. The SiO2 300 nm on p-type silicon is selected as the substrate. 5 nm Ti and 50 nm Au is deposited by a E-beam evaporator system and patterned by using photolithography. Then the directly grown graphene on sapphire substrates is transferred to the substrate with pre-deposited source/drain contacts. The transfer technique is stated as follows in details. (1) 1.5 m thick PMMA is spin coated on the graphene sample. (2) The sample is heated on a hot plate at 120 oC for 5 min. (3) a small portion of the PMMA/graphene film on the corner is peeled off from the sapphire substrate with tweezers. (4) The sample is submerged into DI water and the complete PMMA/graphene film is peeled off. (5) A 300 nm SiO2/Si substrate with pre-deposited source/drain electrodes is used to scoop up the PMMA/graphene film. (6) Store the sample in dry box for 24 h. (7) PMMA is removed by soaking the sample in acetone for 1 h. (8) Store the sample in dry box for 24 h. (Illustrated in Fig. 3-17)
After the transferring procedure is done, the channel is defined by photolithography and then etched away by the RIE system. Then, the bottom-gated
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(a) (b)
(c) (d)
(e) (f)
(g) (h)
Fig. 3-17. The process flow chart graphene transfer process.
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Sample No. 07 08 09 10
Bottom gate metal ○ ○ ○ ○
SiO2* ○ ○ ○ ○
Source/Drain Metal ○ ○ ○ ○
ALD Al2O3 (Recipe III) ○ ○ ○
Top gate metal ○ ○
Measurement structure Bottom-gated Bottom-gated Bottom-gated Top-gated
*: SiO2 is commercially grown on Si.
Table 3-7. Device structure parameters of sequential dual-gated graphene transistor.
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graphene (sample 07) transistor is fabricated. After the ID-VGS characteristic measurement of the bottom-gated transistor, the 30 nm ALD-grown Al2O3 dielectric layer is directly deposited onto the sample. After Al2O3 dielectric layer deposition, the ID-VGS characteristic of the bottom-gated transistor (sample 08) is measured again. After that, top gate metal (5 nm Ti/ 50 nmAu) is deposited by E-beam evaporation and patterned by using photolithography. The finalized dual-gated transistor is investigated for both top- (sample 09) and bottom- gated transistors (sample10). The image of device taken under an optical microscopy is shown in Fig. 3-18. The device structure is shown in Fig. 3-19.
The IDS-VGS curve (Fig. 3-20) of the bottom-gated transistor (sample 07, neither ALD oxide nor top-gate metal is fabricated) shows an n-type doping characteristic. The bipolar current behavior can be clearly seen. The calculated hole mobility value 660 cm2V-1s-1 and electron mobility value 469 cm2V-1s-1 are observed for the device. The electron mobility is smaller than that of hole, which suggests that the thermally grown SiO2 contains electron traps. The IDS-VGS curve of bottom gated transistor after the Al2O3 growth by using ALD (sample 08, top-gate electrode is not fabricated yet) is shown is Fig. 3-21. First, the mobility values of hole and electron are both enhanced.
The hole mobility is increased from 660 to 993 cm2V-1s-1; the electron mobility is increased from 469 to 911 cm2V-1s-1. The enhancement suggests that the Al2O3 layer can
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Fig. 3-18. Optical image of dual-gated graphene transistor.
(Top view. LG = 30 m; W= 10 m)
Fig. 3-19. Device structure of dual-gated graphene transistor.
30 m 10 m
50 m
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Fig. 3-20. IDS-VGS curve of sample 07 (bottom-gated transistor).
Fig. 3-21. IDS-VGS curve of sample 08 (ALD Al2O3 on bottom-gated transistor)
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act as a passivation layer for the underlying graphene channel. Also, the transistor turned out to present a more p-type doping characteristic. This is suggesting that the process during ALD can eliminate the adsorption of H2O molecular, which resulting in n-type doping of the graphene transistor. Therefore, the intrinsic p-type doping of our graphene transistor is revealed [29]. After the top-gate metal is deposited, the result for both top- and bottom- gated transistors are shown in Fig. 3-22 and Fig. 3-23, respectively. The bottom-gated transistor (sample 09) performance is first investigated.
The hole mobility is degraded from 993 to 81 cm2V-1s-1, while the electron mobility is degraded from 911 to 268 cm2V-1s-1. The Dirac point is shifted from -40 to -70 V. The results reveal device performance degradation for the bottom-gated transistor after top-gate metal deposition. We believe that the heat introduced during the metal deposition procedure is responsible for this phenomenon. The higher substrate temperature enables graphene to interact with the oxygen atoms in either the SiO2 or the Al2O3 layers and form graphene oxide, which has lower conductivity than graphene and thus decrease the mobility value. Then the top-gated transistor of the dual-gated structure is investigated. The mobility is 28.2 cm2V-1s-1. The Dirac point is also move to negative region (not observed due to oxide breakdown). The bipolar characteristic is not clearly seen because the oxide is not endurable enough under high voltage after the top-gate metal deposition. We have summarized the results in Table 3-8.
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Fig. 3-22. IDS-VGS curve of sample 09 (bottom-gated transistor of dual-gated structure).
Fig. 3-23. IDS-VGS curve of sample 10 (top-gated transistor of dual-gated structure).
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Sample No. 01 02 03 04 05 06 07 08 09 10
ALD Oxide
Recipe No. I II III IV V VI * * IV IV
Hole Mobility
h (cm2V-1s-1) 5.9 12.8 15.4 N/A 3.1 1.6 660 993 81 N/A Electron Mobility
e (cm2V-1s-1) 2.2 1.0 13.6 N/A 2.7 1.9 469 911 268 28.2 Dirac Point (V) 0.5 1.5 0 N/A -12 -12 12 -44 -78 N/A
*: Gate dielectric SiO2 is commercially grown on Si.
Table 3-8. Comparison and summary of graphene transistors. (Forward Swing).
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