Chapter 6 Models of Sigma-Delta Modulator Power Consumption
6.2 Digital Power Consumption
The digital power consumption is mainly from the clock generator when decimation filter and anti-filter doesn’t be considered. As we know the dynamic power dissipation is the mainly power dissipation of CMOS logic gates and related to their loading capacitors. Fig. 6.1 shows a clock generator with non-overlapping clocks which is connected to an external oscillator, and observing obviously that it is mainly composed of a lot of inverters [Gee02].
The average dynamic power consumption of a CMOS inverter gate can be written as
2 DD Logic S
dynamic f C V
POW = ⋅ ⋅
where CLogic is the loading capacitors of CMOS logic gates. Assuming a clock generator has
N C CMOS inverters and all inverters have identical capacitance of CLogic, then the dynamic power consumption of clock generator is
2 DD Logic S C
CLOCK N f C V
POW ≅ ⋅ ⋅ ⋅
Another important source of the digital power dissipation is from CMOS transmission gates in the switched-capacitor circuits. The output of the clock generator is connected to the gate of the CMOS switches in the switched-capacitor circuits. The CMOS switch is shown in Fig.
6.2. Assuming that the number of the CMOS transmission gate in Σ∆ modulator is NS and the gate capacitances of all CMOS transmission gates are CLogic, and which can be written as
Fig. 6.1. A clock generator with non-overlapping clocks
L W C
Cgate = OX ⋅ ⋅ (6.6)
where COX is the capacitance per unit area of the gate oxide. Wand L are the width and length of the gate oxide respectively. COX can be written as
OX OX
OX t
C ε
=
where the permittivity εOX =3.9ε0 for SiO2 and ε0 is the permittivity of free space, 10 14
85 .
8 × − F/cm. The parallel resistance for the of NMOS and PMOS is
(
DD tn tp)
n OX n switch
V V L V
C W R
−
−
⋅
⋅
⋅
= µ
1 (6.7)
(6.6) employs the supposition as
p OX p n OX
n L
C W L
C W
⋅
⋅
=
⋅
⋅ µ
µ
Combining (6.6) with (6.7) Cgate can be expressed as
( )
2 min gate
n CMOS DD tn tp
C L
R V V V
=µ
⋅ ⋅ − −
The power consumption for all the transmission gates is
2 DD gate S S
Switch N f C V
POW = ⋅ ⋅ ⋅ (6.8) Finally, the total digital power consumption is
Switch CLOCK
digital POW POW
POW = + (6.9) The total power consumption in signal-loop Σ∆ modulator is
digital ana
total POW POW
POW = log+ (6.10)
7
Design Optimization of Sigma-Delta ADCs Design
Power, noise and distortion models derived in Chapter 4, 5 and 6 are employed to systematically discuss how each design parameter affects the SNDR and power consumption.
After identifying critical parameters, we will use them to do design optimization, in order to search for parameter optimal combinations. Before the discussions, we formally define the peak SNDR at Σ∆ ADC output as
DAC NFDCG
settling OTA
sw jitter dac AV
Q
in
HD HD
HD P
P P P P P P P
A
SNDR= + + + + + + + + + +
2 1
2
2 ) 2 (
ε ε
（7.1）
7.1 Design Parameters Discussions
Based on models in Chapter 4, 5, and 6 the influences of each design parameter to the SNDR and Power are discussed in the following:
1. OSR can influence the behavior of all nonidealities and power consumption. Higher OSR is helpful to reduce settling distortion. But, OSR is proportional to the digital power consumption according to（4.42）.
2. B is an important system parameter. Higher bit number results in smaller quantizer level and relaxes the dynamic requirement of OTA. But, the settling distortion doesn’t change with B and higher B will introduce significant DAC distortion. Both the DAC noise power （4.36）and the digital power consumption（4.43）increase exponentially with B.
3. n is the order of a Σ∆ modulator. Increasing n will increase the value of AVS such that it will increase the settling distortion.
4. A0 is the open loop gain of OTA. Finite A0 will cause nonlinear op-amp gain distortion. Simulation shows that a minimum required A is about 60 dB.
5. a1=C CS I is the gain coefficient of the first integrator, and usually varies from 0.1 to 1.
6. R is the on-resistance of switches. The on-resistance of switch S1 is dependent on the input signal, so it produces harmonic distortions. Appropriate design can be obtained to have negligible harmonic distortions.
7. GBW means the effective gain bandwidth of OTA during integration phase. A larger GBW can reduce the settling distortion, but increase analog power consumption（4.41）. 8. CS is the capacitance of sampling capacitor. Its value depends on the stored voltage
slightly so it produces little harmonic distortions.
9. VOS is the maximum output swing of OTA. It effects nonlinear finite OTA gain distortion size.
10. SR is the OTA slew rate and plays an important role in integrator output settling performance. The larger SR, the smaller settling noise and distortion is.
11. σcap is the standard deviation of unit capacitor and its value depends on process technology. Recently, double poly and metal-insulator-metal (MIM) capacitor are the two main methods to implement capacitors in analog integrators circuits. These two types of capacitors have high linearity and good matching accuracy, and σcap of them are all below 0.05%. The main influence of σcap on Σ∆ modulators is the multi-bit DAC linearity.
PQ
PAV
Pref
POTA
Psw jitter
P Pdac ε1
P
ε2
P
HDDAC
σcap
CS
NFDCG
HD
VOS
settling
HD
Table 7.1 Summary of noise and distortion-power and power-rating when design parameters increase
In Table 7.1, PQ is the quantization noise. PAV is the leaky quantization noise.
ε1
P is the
setting error during the sampling phase.
ε2
P is the setting error during the integration phase.
Pdac is the DAC noise. Pjitter is the jitter noise. Psw is the switch thermal noise. POTA is the OTA thermal noise. P is the reference circuits thermal noise.ref HDsettling is the settling distortion. HDNFDCG is the nonlinear finite-OTA-gain distortion. HDDAC is the DAC distortion. Table 7.1 summarizes the above discussions. Basically we identify B, OSR, n, R, GBW, CS and SR as the optimization process design parameters. Table 7.1 shows qualitatively how distortion and power are affected when a particular design parameter increases, and it reveals that the Σ∆ ADC design task is a very complex one.
7.2 Design Optimization
In the following we describe the design optimization approach and it will help designers reach an optimal design quickly. It is based on the noise, distortion and power models described in Chapter 4, 5 and 6. The complete flow of the optimization methodology is shown in Fig. 7.1. The input signal bandwidth (Hz) and the output signal SNDR (dB) are treated as design specifications. We modify the figure-of-merit (FOM) [Sch 05] function by multiplying a variable K to the SNDR term of FOM, to become our weighting function.
Weighting Function =
+
⋅ Power
SNDR f
K dB 10log B （7.2）
Fig. 7.1 Proposed design optimization for the Σ∆ modulator design
In（7.2）the SNDR and the inverse of Power are both expressed in log scale. The design optimization approach basically searches through the entire parameter space to find the set of design parameters which maximize the Weighting Function. By maximizing the Weighting Function we can increase SNDR（7.1）and reduce Power（4.45）at the same time. The constant K serves as the relative weighting between SNDR and Power. A larger K would result in a larger SNDR and Power. Some optimization iterations may be required. Typically, if we prefer high resolution designs, we set K higher and SNDR plays a more important role than Power;
on the other hand, if we prefer low power designs, we can set K lower. After an optimization process, the set of design parameters resulting in the largest Weighting Function value is the process outcome and is evaluated. If not acceptable, the K is adjusted and the optimization process is repeated. The parameter searching space is specified to be
OSR : 8 ~ fB
⋅ 2
MHz 80
B : 1 ~ 6
n : 1 ~ 3
R : 100 Ω ~ 300 Ω
GBW : 50 MHz ~ 500 MHz
SR : 50 V/µs ~ 500 V/µs
CS : 1 pF ~ 10 pF The parameters σcap and
Vref depend on the technology, so they are set before the optimization. During the optimization process, the gain coefficients ai are specified according to the rules provided in [Mar 98b]. The optimization algorithm systematically searches the entire parameter space listed above.
8
Simulation Results
The design optimization described above is implemented by Mathematica®. In order to demonstrate the accuracy and practicability of our models, we apply it to a published design case, which is a Σ∆ modulator in 0.18-um CMOS technology for ADSL-CO application [Gag 03]. Its peak SNDR can reach 78dB over 276kHz signal bandwidth.
To compare with the design of [Gag 03], the optimization algorithm uses the same specifications as those in [Gag 03]. They are:
Peak SNDR : 78 dB
Signal bandwidth : 276 kHz
The OTA gain A0 is set at 60 dB and the Vref is set at 0.9 V for a 1.8 V power supply in
0.18-µm CMOS technology. The matching of capacitor σcap is set at 0.04% for the MIM capacitance. VOS is set at 1V. The parameter variable ranges are also specified as follows. For the signal bandwidth of 276 kHz, the range of OSR is set between 8 ~ 128, and the quantizer bit B is between 1 ~ 5. The order n is between 1 ~ 3, since using a n higher than 3 may cause instability. The R range is between 100 Ω ~ 300Ω. CS is between 1 pF and 10 pF. The
minimum size of CS is usually determined by process technology. Finally, GBW and SR are between 50 MHz ~ 500 MHz and 50 V/µs ~ 500 V/µs respectively. The results published in [Gag 03] and those obtained from our optimization methodology are all listed in Table 8.1, which includes three optimization results corresponding to K=0.5, K=2, and K=5.
circuit parameters Ref [Gag03] K=0.5 K=2 K=5 Unit
OSR 96 32 64 128 -
B 3 3 3 3 -
n 2 2 2 2 -
R 300 300 100 100 Ω
CS 1.7 1 1 1.2 Pf
CL2 7.2 5.8 5.8 6.2 pF
GBW 400 70 130 280 MHz
SR 500 88 163 352 V/µs
σjit 9 9 9 9 Ps
Ain at peak SNDR 0.75 0.9 0.9 0.75 V
Peak SNDR 77.2 74.5 76.4 77.7 dB SNDR
(SIMULINK) 78 75 77.2 78.2 dB
total
POW 14 3.4 6.7 13.9 mW
Table 8.1. Comparisons of our design results with the measurement in [6]
From Table 8.1, when K = 0.5 and K=2, the SNDR are lower than the specification. In order to increase SNDR, we need to increase K. When K=5, the theoretic result of SNDR = 77.7dB approach the specification, and the behavior simulation result of SNDR = 78.2dB satisfy the specification. The POWtotal= 13.9mW for K=5 is almost equal to POWtotal for Ref[Gag03].
When K=5, although OSR needs to be larger than the one in Ref[Gag03], but the demands for GBW and SR are much lower, and reduce the complexity for OTA design.
Table 8.2 shows the corresponding noise and distortion powers for the four design cases shown in Table 8.1. In the design of [Gag 03], and in our designs for K=0.5, 2, 5, the dominating power is Pdac and HD2DAC. Due to the DEM is not employed, so the above two nonlinearities power can’t be reduced effectively. Although SNDR of our theoretic result can’t be higher obviously in this case, but our proposed optimization result offers another way to obtain the suitable circuit specifications fast.
Table 8.2. The corresponding noise powers for the design parameters listed in Table 8.1
Table 8.3 Listing the details of power consumption.
Table 8.3 lists the power consumption details. In POWanalog, POWΣ∆_OTA consumes the most much power, hence we analysis the analog power consumption for OTAs. From（6.1）, we can see that the POWΣ∆_OTA is proportional to the GBW and CL2. The CL2 （4.19）is proportional to the sampling capacitance CS. From Table 8.1, we can see that the GBW of [Gag 03] is larger than that of K=0.5, K=2 and K=5 and CS of [Gag 03] is larger than those of the all theoretic results. Hence, the POWΣ∆_OTA of [Gag 03] is the largest among the four cases. From（6.8）, we can see that the POWClock and POWSwitch are both proportional to the sampling frequency fS, hence
digital
POW for K=5 is the largest among the for cases since Nonlinearities
Power Ref [Gag06] K=0.5 K=2 K=5 Unit
PQ - 109.8 - 84.9 - 89.8 - 105.8 dB
PAV -141.1 - 123.6 - 126.5 - 141.0 dB
ε1
P - 196.5 - 681.7 - 551.5 - 258.4 dB
ε2
P - 119.3 - 103.9 - 104.5 - 120.0 dB
Psw - 96.9 - 90.8 - 91.8 - 95.6 dB
Pref - 114.7 - 101.0 - 103.1 - 109.1 dB POTA - 117.0 - 110.9 - 111.9 - 115.7 dB
Pdac -79.6 -74.9 -78 -81 dB
NFDCG
HD3 -108 -91.2 -96.6 -110.5 dB
settling
HD3 -130.6 -108.6 -17.6 -110.7 dB
settling
HD5 -145 -131 -126.6 -127.6 dB
HD2DAC -80.1 -77.7 -77.7 -80.1 dB
HD3DAC -91.7 -87.6 -87.7 -91.8 dB
HD4DAC -106 -100.2 -100.2 -106.1 dB
Ref [Gag06] K=0.5 K=2 K=5 Unit
log
POWana 8 1.4 2.7 5.9 mW
digital
POW 6 2 4 8 mW
which has the largest OSR.. If SNDR must to be increased, Pdac can be reduced effectively and HDDAC can be eliminated by employing DEM techniques, but POWdigital becomes larger.
9
Conclusions and Future Works
In order to increase the speed of circuit design for Σ∆ ADCs, this paper offers an efficient optimization method to obtain the most suitable circuit specifications. All the nonlinearity power also can be obtained after an complete optimization, and the dominating nonlinearity power can be reduced by adjusting the design specifications. Our proposed method has acceptable accuracy and nice speed, and the flexibility can be enhanced by building more nonlinearity models for different circuit structures.
Further, in order to reduce the time-cost for optimization, the algorithm efficiently search the entire design parameters space to find the parameter set which satisfies the specifications must to be established.
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