Chapter 4 A Low Power Digital Automatic Gain Control for Audio
4.2 Digital AGC System Design
The Proposed Digital AGC
Figure 4-1 is the proposed dual-loop digital AGC. It includes a VGA, a
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
sigma-delta modulator, a bit-stream rectifier, a sinc filter, a low-pass filter (LPF), integrators, a value mapping (VM) block, and a DAC. It is different from the traditional digital AGC shown in Figure 2-8. The feedback point is at the output of the modulator rather than the output of ADC. It does not go through a decimation filter.
Therefore, this architecture has a lower latency, power, and area than the traditional one. The AGC is programmable and does not design the integrators and the LPF by off-chip capacitors. The circuits of the feedback loop of the AGC are designed easier than the analog AGCs’ in low voltage. To achieve requirements of the attack time and the release time, the dual loop architecture is used in this design. The modulator has been introduced in Chapter 3.
Vout
Figure 4-1 The proposed dual-loop digital AGC
Design specifications
The specifications of the AGC are listed in Table 4-1. The input signal bandwidth is designed in audio bandwidth from 250 Hz to 10 kHz. It covers the speech bandwidth. The total harmonic distortion (THD) must be less than 5%. It is enough for the intelligibility of speech signals. The maximum output amplitude of the AGC is designed as 0.3V because the input signal of the modulator at the peak SNR is 0.3V.
The AGC also avoid the instability of the modulator. Form (2.5), Vref is designed as 0.191V. The SNR of the AGC is designed as 74dB. The attack time is less than 5ms and the release time is about 50ms. The specifications of the modulator have been introduced in Chapter 3. The microphone sensor is SP0102N of Knowles. The output voltage range of the microphone is form 12.6uV to125mv. It equals the sound
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
pressure level (SPL) form 35dB to115dB.
Table 4-1 Specifications of the proposed AGC
Spec. Performance Value Unit
Audio Frequency Range 250 – 10k Hz
Output Voltage Range 12.6u - 125m V Microphone
(Knowles SP0102N) Input Sound Range 35-115 dB
Simulation results of a analog AGC
To design the digital AGC, an analog AGC shown in Figure 2-6 must be designed first. The coefficients are obtained by simulating the analog AGC. Then the digital AGC is designed by the parameters.
There are two nonlinear features in Figure 2-6. One is that V will be saturated o when the input signal becomes large suddenly. Another is that KVGA is dependent on V . The transfer function between o Vref and Vout of the analog AGC has been which is obtained from the VGA circuit. The maximum output amplitude of the VGA is 0.1V and the maximum input amplitude of the modulator is 0.3V. Thus KGB is designed as 3. The average detector gainKAP is 2 /π which has been introduced from (2.5). However, the p and 1 ωu, which represents ωuaor ωur, factors must be designed. When p is increased, 1 ωn and ξ will be increased. When ωu is increased, ωn and ξ will be increased and decreased, respectively. The analog
AGC is designed by these properties. Finally, / ) ω
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
is obtained as180(rad s , / ) ωur is obtained as22(rad s , and / ) V is derived as L 0.15 | 1400 | 0.061 ( )
2 500 1400 V
j π
× =
× +
It means that the rectifier output signal with the lowest frequency of 500 Hz and the maximum amplitude of 0.15V will obtain a Voltage of 0.061V at the LPF output. It hopes that the output signal amplitude is not decreased in low frequency. When the input signal changes suddenly between 5.6mV and 100mV at the frequency of 250 Hz, the simulation result is shown in Figure 4-2. The attack time is 3ms and the release time is 51ms.
Figure 4-2 The simulation result of the analog AGC at frequency of 250 Hz When the input signal changes suddenly between 5.6mV and 100mV at the frequency of 10 kHz, the simulation result is shown in Figure 4-3. The attack time is 3ms and the release time is 51ms.
Figure 4-3 The simulation result of the analog AGC at frequency of 10 kHz
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Figure 4-4 shows the input SPL versus the output amplitude. When the SPL is more than 88 dB, the AGC output amplitude will be pulled to -10.5dBV. When the SPL is less than 88 dB, the AGC input signal will be linearly amplified by the constant gain of 25dB. The SPL of 115dB represents a voltage of 125mV.
35 88
−63.5
−10.5
115 Input (dB SPL) AGC Output Amplitude(dBV)
Figure 4-4 Input SPL versus output amplitude for the proposed AGC
4.3 Digital AGC System Design
Bit-stream rectifier design
Figure 4-5 shows the one-order sigma-delta modulator. When the input signal is positive, the pattern of -1-1 will be not occurred. When the input signal is negative, the pattern of 11 will be not occurred. The simulation result is shown in Figure 4-6(a) where the sinusoid wave is the input signal and the pulse wave is the output of the one-order modulator.
1 1 1
Z Z
−
− −
−1
Vin Vout
Figure 4-5 One-order sigma-delta modulator
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Figure 4-6 (a) The one-order SDM output signal (b) The rectifier output signal Using these pattern properties, a bit-steam rectifier will be designed by Table 4-2. If the output bit of the one-order modulator represents a zero-average amplitude information, the rectifier output will obtain 0. If the output bit represents an amplitude information, the rectifier output will obtain 1. The simulation result of the rectifier table is shown in Figure 4-6(b). It shows that the original pulse wave signal becomes the positive signal.
Table 4-2 Rectifier table for 1-order SDM Series (Vout) Result
n n+1 n
1 -1 0
-1 1 0
1 1 1
-1 -1 1
For a high-order sigma-delta modulator, the patterns of -1-111 and 11-1-1 will be occurred when a small input signal is imported. The simulation result of the third-order modulator is shown in Figure 4-7(a). These patterns are occurred in dotted-line circles.
1
-1 1
0
(a)
( b )
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Figure 4-7 (a) Third-order SDM output signal (b) Rectifier output signal
These patterns represent a zero-average amplitude information. When Table 4-2 is used only, it will not obtain the zero-average amplitude information. So an additional table must be used. It is listed in Table 4-3. Using this additional table, the simulation result of the rectifier table with the additional rectifier table is shown in Figure 4-7(b).
Table 4-3 Additional rectifier table for high-order SDM
Series (Vout) Result
n n+1 n+2 n+3 n n+1 n+2 1 1 -1 -1 0 0 0 -1 -1 1 1 0 0 0
In Figure 4-9, the transverse axle is the input sinusoid signals with the amplitude from 0V to 0.5 V at the frequency of 1 kHz. The signals are imported to a third-order sigma-delta modulator. Then the rectifier output obtains the output signals of the modulator. The average value of the rectifier output which represents a LPF output signal at DC is multiplied by π/ 2, and it represents the detected amplitude. The result shows that the proposed bit-stream rectifier works well.
1
1
0
( a ) -1
(b)
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Figure 4-8 Simulation result of the proposed bit-stream rectifier
Low Pass Filter
Figure 4-9 includes a sinc filter and a LPF. The sinc filter filters the input signal roughly. The main purpose is to down the clock frequency. The sinc filter is a simple circuit, and it operates at high frequency. The LPF is a complex circuit, and it operates at low frequency. Thus, the power consumption of this architecture is lower than the architecture of only a low pass filter.
Vin Vout
Figure 4-9 The architecture of low pass filter The transfer function of the sinc filter is represented as
1
Input Signal Amplitude (V) @ 1 kHz
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit It shows that the sinc filter decays a little gain at the 3dB bandwidth. The effect is ignored. The z-domain model of the sinc filter is shown in Figure 4-10. It also shows the bit numbers of the paths. The bit numbers of the input is one, and the bit numbers of the output is eight because that Vref is designed as 8 bit. When a value one is imported only, the output will obtain the maximum value of 0.5.
Vin
Figure 4-10 Z-domain model of the sinc filter
From Section 4.2, The Z-domain transfer function of the LPF is derived as (4.5) by Foreward Euler and the sampling frequency is10 kHz.
1 To design it as a circuit, the parameters need to be quantized. The quantization result is shown in Figure 4-11 where A is a binary value of (0.001001)2. The quantization method is like to Canonic Sign Digit (CSD). It has the minimum number of non-zero digits. So a number of adders are decreased. Figure 4-11 also shows the paths with bit numbers and maximum value.
A
Figure 4-11 Z-domain model of the LPF
The comparison of the non-quantization LPF and the quantization LPF is shown in
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Figure 4-12 where the continuous line and the star line represent spectrums of the non-quantization LPF and the quantization LPF, respectively. Test signals at the frequencies of 19.53Hz, 195.3Hz, and 1953Hz are imported. It shows that they match well.
Figure 4-12 Non-quantization LPF versus quantization LPF
Integrator and value mapping
From Section 4.2, the Z-domain transfer functions of the integrators are derived as (4.6) and (4.7) by Foreward Euler and the sampling frequency of 10 kHz.
1 respectively. In terms of value mapping block, the maximum and minimum output values of the integrators are 0.1468 and -0.05, respectively. The value 0.1468 maps to the value 111111 at the DAC input. The value -0.05 maps to the value 000000 at the DAC input. So the mapping equation between the integrator output and the DAC input is derived as needs to cost some adders.
(Hz)
(dB) 19.53 Hz 195.3 Hz
1953 Hz
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
It needs only two adders to realize it. So the VM area will be decreased. The Z-domain models of the integrators and the VM are shown in Figure 4-13 where S is the selection signal of MUX, V is the input signal of the integrators, and in Vout is the output signal of the VM.
Figure 4-13 Z-domain model of integrators and VM