Chapter 4 A Low Power Digital Automatic Gain Control for Audio
4.4 Variable Gain Amplifier
Variable Gain Amplifier
In an AGC loop, to maintain its settling time independent of the input signal levels, an exponential gain control characteristic is required. Unlike the exponential characteristic of the bipolar transistors, which is very suitable for dB-linear AGC, CMOS transistors follow a square-law characteristic in strong inversion. Although the transistors present exponential characteristic in weak inversion, their area is large at large current. Thus, some of the reported CMOS dB-linear VGAs are based on a pseudo-exponential function [13] given by
1 2 The approximation errors of this pseudo- exponential function to ideal one is within 5% only when x <0.32.
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Figure 4-14 Variable gain amplifier
There are two types of VGA, which are current-mode and voltage-mode VGAs.
The current mode VGAs are presented in [15] and [16]. But they are hard to be used in reality due to need a current to voltage converter and a voltage to current converter.
The offset voltage in the current mode VGAs is also a seriously problem. Figure 4-14 is a voltage-mode VGA circuit [14] where V is a gain control signal. The VGA is c used in this design due to be designed easily in low voltage. This architecture has a fully-differential output and a single-end input
Using (4.10) to approximate the exponential function, the gain equation for the VGA in Figure 4-14 is derived as
( )
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Common Mode Feedback
There are two types of common-mode feedback (CMFB) [1]. One is a continuous circuit, and another is a switched-capacitor circuit shown in Figure 4-15. In a low voltage environment, the latter is chosen. Because it does not affects the swing of a amplifier and is designed easily in low voltage. In terms of the power consumption, it consumes only the dynamic power and so this circuit has a lower power consumption.
The equivalent equation of the switched-capacitor CMFB is derived as 2
o o
b bias refa
V V
V = ++ − +V −V (4.13) It shows that the CMFB output generates a common mode voltage. It is fed back to the amplifier. Thus, the output common mode voltage of the amplifier will be controlled by this voltage.
Figure 4-15 Common mode feedback
Output Buffer and Bias Circuit
The driving ability of the VGA is not enough. One main reason is that the VGA drives a next stage circuit by the variations of the drain-to-source voltage of MOSs.
To obtain a better driving ability, Figure 4-16 is used. This circuit will decrease the gate voltage of M when the output charges a load capacitor. It will increase the 3 gate voltage of transistor M when the output discharges the capacitor. So it has a 3 higher power efficiency.
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Figure 4-16 Output buffer for the VGA
The bias circuit [3] is shown in Figure 4-17. The resistor is designed between VDD and the drain of PMOSM . PMOS 4 M avoids such body effect that this 4 circuit is designed easily in low voltage. The bias circuit has two stable conditions.
One is the bias circuit in work state, and another is the all transistors of the bias circuit in off state. So a start-up circuit must be designed. When the power supply is on initially,Ms3will be on. The gate voltage of Ms1is given by VDD. After transistor
s1
M is conducted, the bias circuit is revived. Then the gate ofMs2obtains a operational voltage such that the drain of Ms2obtains a low voltage. Finally, Ms1is in off state. So the start-up circuit does not affect the bias circuit at the bias circuit in work state. The channel resistance of Ms3 must be designed large.
Figure 4-17 Bias circuit
Simulation Results
The gain versus the control voltage of the VGA is shown in Figure 4-18. It shows that the relationship between the control voltage and the gain is exponential. The
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
tuning range of the gain is 33.5dB. The range of the control voltage is 0.197V. From (2.3) and Figure 4-17, α is calculated as 19.58 and so KVGA is 19.58V . o
Figure 4-18 Gain versus control voltage
In order to have the enough the intelligibility of speech signals, the THD of sound signals must be less than 5%. The THD versus the sound pressure level (SPL) is shown in Figure 4-19. The THD is less than 4.1% when the SPL is less than 115dB.
Figure 4-19 THD versus SPL
The microphone Specifications are shown in Table 4-1. When the output voltage is 63mV, the SNR will be 74dB. It represents to have 12-bit resolution. Thus, a test sinusoid wave of 63mV is imported to the VGA input. In this condition, the VGA gain is 4dB because this input signal will be amplified as 100mV, witch is the maximum amplitude of the VGA. In order to obtain a SNR of 74dB for the VGA, the minimum noise power requited is calculated as follow.
(Vc=0.45, Gain= -8.5 dB) Gain(dB)
THD (%)
SPL (dB) Vc (V) (Vc=0.647, Gain=25 dB)
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit input noise power of the VGA from 250Hz to 20 kHz is calculated as
20
Figure 4-20 Noise power versus input frequency at gain 4dB
When the control voltage is changed, the input noise power of the VGA will be changed. The minimum noise power occurs at the maximum gain which has the maximum inputg . In this condition, a small signal is imported. In Figure 4-21, the m noise RMS voltage is calculated as (4.16) when the gain is maximum.
20
250k inn( ) 3.75 HzP f df = uV
∫ . (4.16) The maximum RMS voltage is calculated as 88mV below the THD of 4.1% . So the dynamic range of the VGA is derived as
Chapter 4 A Low Power Digital Automatic Gain Control for Audio Front-End Circuit
Figure 4-21 Noise power versus input frequency at gain 25dB