Effect of various fluorine dose

Fig. 2.13 shows the ID-VG at small drain voltage (VDS=100mV) transfer characteristic of the CESL strained devices with fluorine dose are 1E12cm^-2, 1E13 cm^-2, 1E14 cm^-2, respectively. (where the device channel length and width were 0.3 and 10µm, respectively.) Unexpected, the improvement of the drain current,

transconductance and subthreshold swing do not change for the better with increasing fluorine doses. The subthreshold swing are 96mv/dec (1E12 cm^-2), 98mv/dec (1E13 cm^-2), 108mv/dec(1E14 cm^-2), respectively. We can observe that when fluorine dose is 1E12 cm^-2, the improvement effect is the best.

The ID-VD output characteristic of the the CESL strained HfO2/SiON nMOSFETs devices with fluorine dose (1E12cm^-2, 1E13cm^-2, 1E14cm^-2, respectively.) are compared in Fig. 2.14 where the device channel length and width were 0.3µm and 10µm, respectively. The experimental also shows the same result is that as fluorine dose more than 1E12 cm^-2, the basic characteristic degrade with increasing fluorine.

And Fig. 2.15 displays the gate leakage current versus gate voltage (IG-VG) characteristic under inversion and accumulation mode. The result is not obviously different. We surmise that because redundant fluorine ions will band with hydrogen ions, resulting in worse performance. Therefore, the following discussion will not consider SSFI B and SSFI C due to their worse performance.

2.3.3 Current Transport Mechanism

Fig. 2.16 (a) and (b) and (c) show gate current IG as a function of VG for the HfO2/SiON gate stacks with TEOS P.L, SiN P.L and fluorinated SiN P.L ,respectively.

They were measured at several different temperatures up to 100°C in inversion and

accumulation regions. The current is temperature dependent that increases with increasing temperature. This implies that the conduction mechanism of gate current is trap-related, i.e., trap-assisted tunneling (TAT), Frenkel-Poole, etc. Base on the equation of Frenkel-Poole (F-P):

Where B is a constant in terms of the trapping density in the HfO2 film, ΨB is the barrier height, E_ox is the electric field in HfO₂ film, is the free space permittivity, is the HfO₂ dielectric constant, K_B is Boltzmann constant and T is the temperature measured in Kelvin. Fig. 2.16 (a), (b) and (c) show the F-P plot for the source/drain current in inversion region for the control device and the strained without and with fluorinated, respectively. Fig. 2.17 (a), (b) and (c) show the F-P plot for the substrate current in inversion region for the control device and the strained without and with fluorinated, respectively. These lines are fitting curves for all temperatures. In the high voltage I_SD and I_SUB, an excellent linearity for each current characteristic can be obtained, indicating that the control device and the strained without and with

in nature.

The barrier height ΨB can be calculated from the intercept of y axis and the

dielectric constant of HfO₂/SiON gate stacks can be determined by the slope of the fitting curves according to Equation(2.3). On the other hand, the fitting parameters for the electron and hole barrier heights are 1.07eV and 1.36eV for the TEOS sample.

The strained sample are1.2eV and 1.49eV, as compared to1.19eV and 1.5eV for the strained sample with fluorinated. Note that the barrier height for electrons has changed from 1.07eV for TEOS sample to 1.2eV for SiN sample and 1.19eV for strained SSFI sample, and for holes has changed from 1.36eV for TEOS to 1.49eV for SiN sample and 1.5eV for strained SSFI sample. This indicates that the trap position has moved closer to the conduction and valence band of the poly-si gate after strain process. The band diagrams are shown in Fig. 2.19 (a), (b) and (c) for the HfO₂/SiON gate stacks with TEOS P.L, SiN P.L and fluorinated SiN P.L, respectively. Because precursor of SiN sample is NH₃, nitrogen atoms could recover shallow traps. SiN samples with SSFI have fluorine atoms and it could recover shallow traps, similarly.

Therefore both of them have deeper trap level than TEOS P.L. We consider the case

when the injected carriers flow across HfO₂/SiON by hopping via the trap sites with energy barrier Ψ_B whose value depends on the fabrication process [4].This

experimental results indicate that the position of traps level in the strained sample

with and without SSFI can be deeper than the TEOS sample, and the energy barrier ΨB for electrons is clearly lower than that for holes about 0.3eV in these samples.

2.4 Summary

In this chapter, a novel CESL strained high-k dielectric with implantation fluorine was presented. We have performed a systematical investigation of electrical characteristics. Significant device performance improvement in strained devices with and without fluorinated were found, such as the excellent subthreshold swing, increased transconductance, higher current drive, improved channel electron mobility, as compared to the control TEOS sample. These results suggest us that optimize fluorine incorporation (1E12cm^-2) does not degrade basic electrical characteristic from strained effect. However, too much fluorine ions will degrade performance because of fluorine ions bending with because hydrogen ions.

Finally, the control device and the strained without and with fluorinated devices exhibit the F-P conduction mechanism for the gate leakage current in nature.

2.5 References

[1] H. J. Cho, C. Y. Kang, C. S. Kang, R. Choi, Y. H. Kim, M. S. Akbar, C. H. Choi, S. J. Rhee, and J. C. Lee, “The effects of nitrogen in HfO/sub 2/ for improved MOSFET performance”, IEEE semiconductor Device Research Symposium.

[2] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks, “ J. Appl.

Phys. Vol. 93, pp.9298, 2003

[3] E. Gusev, D. A. Buchanan, and E. Cartier, “Ultrathin high-K gate stacks for advanced CMOS devices”, IEDM Tech. Dig., pp451,2001

[4] M. D. Giles, et al., “Understanding stress enhanced performance in Intel 90nm CMOS technology,” VLSI Symp. Tech. Dig., 2004, pp. 118-119.

[5] K. Mistry, et al., “Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology,” VLSI Symp. Tech. Dig., 2004, pp. 50-51

[6] K. T. Lee, et al., “A compressive study of reliability and performance of strain engineering using CESL stressor and mechanical strain,” IRPS Symp., 2008, pp.

306-309

[7] H.-H. Tseng, P. J. Tobin, E. A. Hebert, S. Kalpat, M. E. Ramon, L.Fonseca, Z. X.

Jiang, J. K. Schaeffer, R. I. Hedge, D. H. Triyso, C.C. Capasso, O. Adetutu, D.

Sing, J. Conner, E. Luckowski, B.W.Chan, A. Haggag, S. Backer, R. Noble, M.

Jahanbani, Y. H. Chiu,and B. E. White, “Defect passivation with fluorine in aTaxCy/high- gate stack for enhanced device threshold voltage stability and performance,” in IEDM Tech. Dig., 2005, pp.696–699.

[8] M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K.Shiga, J.

Yugami, J. Tsuchimoto, Y. Ohno, and M. Yoneda,“ Fluorine incorporation into HfSiON dielectric for Vth control and its impact on reliability for Poly-Si Gate pFET,” in IEDM Tech. Dig.,2005, pp. 413–416.

[9] K.-I. Seo, R. Sreeenivasan, P. C.McIntyre, and K. C. Saraswat,“ Improvement in high- (HfO2/SiO2) reliability by incorporation of fluorine,” in IEDM Tech. Dig., 2005, pp. 417–420.

pp. 2307-2310, 2005.

[11] T. Yamaguchi, H. Satake, N. Fukushima, “Degradation of current drivability by the increase of Zr concentrations in Zr-silicate MISFET,” IEDM Technical Digest, 2001, p.663

[12] M. V. Fischetti, D. A. Neumayer, and E. A. Catier, “Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-k insulator: The role of remote phonon scattering,” J. Appl. Phys., vol.90,p.4587,2001

[13] T. Yamaguchi, H. Satake, N. Fukushima, and A. Toriumi, “Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Deposition, “IEDM Tech. Dig., pp. 19-22, 2000.

[14] L. Tsetseris, X. J. Zhou, D. M. Fleetwood, R. D. Schrimpf, andS. T. Pantelides,

“Dual role of fluorine at the Si−SiO2 interface ”Appl. Phys. Lett., vol. 85, no. 21, p. 4950, Nov. 2004.

[15] A. Kazor, C. Jeynes, and I. W. Boyd, “Fluorine enhanced oxidation of silicon at low temperatures,” Appl. Phys. Lett., vol. 65, no. 12,pp. 1572–1574, Sep. 1994

[16] H. Miyajima, R. Katsumata, Y. Nakasaki, Y. Nishiyama, and N. Hayasaka: Jpn.

J. Appl. Phys. 35 (1996) 6217.

[17] W. J. Chang, M. P. Houng, and Y. H. Wang: Jpn. J. Appl. Phys. 38(1999) 4642.

[18] C. D. Young, et al., “Electron trap generation in high-k gate stacks by constant voltage stress,” Trans. Device Mater. Rel., vol. 6, No. 2, 2006, pp. 123-131.

Fig. 2.1 Fluorine incorporation via channel implantation

 Stand LOCOS process

 RCA clean and HF dip. wet pre-cleaning

 SiON target ~1nm：RTA 800℃ 30sec in N2O ambient

 MOCVD of 30Å HfO2 (500℃)

 PDA 600℃ 30sec in N2 ambient

 Poly-Si deposition 200nm and pattering

 Extension S/D implant + Space formation + Deep S/D implant

 Dopant activation ： 950℃ 30sec in N2 ambient

 Passivation layer by PECVD Control ： TEOS 4000Å P.L

 Metallization ：Al-Si-Cu 9000Å

 Forming gas sintering ：400℃ 30min

F F

F

F F

F F

F

F F

F

FOX

FOX

 Stand LOCOS process

 Fluorine implantation

Dose：0、1E12、1E13、1E14 Energy ：10KeV

 RCA clean and HF dip. wet pre-cleaning

 SiON target ~1nm：RTA 800℃ 30sec in N2O ambient

 MOCVD of 30Å HfO2 (500℃)

 PDA 600℃ 30sec in N2 ambient

 Poly-Si deposition 200nm and pattering

 Extension S/D implant + Space formation + Deep S/D implant

 Dopant activation ： 950℃ 30sec in N2 ambient

 Passivation layer by PECVD

SiNx 3000Å P.L + TEOS 1000Å P.L

 Metallization ：Al-Si-Cu 9000Å

 Forming gas sintering ：400℃ 30min

Fig. 2.2 The process flow of nMOSFETs with HfO2/SiON gate stack (a) control (b) strained with and without SSFI

Fig. 2.3(b) Schematic cross section of CESL nMOSFETs with HfO₂/SiON gate stack with and without fluorinated

Fig. 2.4 The experimental setup for the basic electrical characteristics and long-term FOX

FOX

S D

TEOS TEOS

30 40 50 60 70 80 90 100 110 120

Fig. 2.5 SIMS depth profile of the HfO₂/SiON gate dielectrics. Fluorine atoms

accumulated mainly at near the HfO2/silicon substrate interface after silicon surface fluorine implantation (SSFI).

Fig. 2.6 The X-ray Photon electron Spectroscopy (XPS) analysis of the F 1s electronic spectra of SSFT treatment samples

680 682 684 686 688 690 F

1S

of the HfO

2

In te n s it y ( a rb . u n it )

Binding Energy (eV)

Fig. 2.7 Hf 4f Electron Spectra Chemical Analysis (ESCA) of (a) without fluorinated and (b) fluorinated, respectively.

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Fig.2.9 The I_D-V_D output characteristic curves of the control nMOSFET and the strained nMOSFET with and without fluorine.

-8 -6 -4 -2 0 2 4 6 8

Fig. 2.10 Gate leakage current as a function of gate voltages of the control nMOSFET and the strained nMOSFET with and without fluorine. Both under inversion and accumulation regions.

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

ControlNitride 1E12 1E13 1E14 3.2 Fig. 2.11 The C-V characteristics of HfO₂ gate dielectrics with various fluorine doses

1 10

Fig. 2.12 The maximum transconductance versus channel length for all splits of

-0.6 -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8

Fig. 2.13 The I_D-V_G transfer and Gm-V_G characteristic of the CESL strained devices with fluorine doses are 1E12cm^-2, 1E13cm^-2, 1E14cm^-2, respectively.

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Fig. 2.14 The I_D-V_D output characteristic of the CESL strained devices with fluorine

-8 -6 -4 -2 0 2 4 6 8 10

^-14

10

^-13

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

L/W=2/10 Control Si

3

N

4

Capping 1E12

1E13 1E14

G a te l e a k a g e c u rr e n t (A )

Gate Voltage (V)

Fig. 2.15 Gate leakage current as a function of gate voltages with various fluorine doses

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

Fig. 2.16 Gate leakage current versus gate bias for fresh n-channel devices at different temperatures (a) TEOS P.L (b) SiN P.L (c) SiN P.L with SSFI

2000 2200 2400 2600 2800 3000 3200

-35

2400 2600 2800 3000 3200 3400

2800 3000 3200 3400 3600 3800 4000 -30

Fig. 2.17 Conduction mechanism for source/drain current fitting under inversion

2800 3000 3200 3400 3600 3800

3800 3850 3900 3950 4000 4050 4100 4150 4200

-30

3800 3900 4000 4100 4200 4300 -30

-28 -26 -24 -22 -20 -18

ln (J

Sub

/E

eff

)

E

^1/2

eff

(V/cm) SSFI(1E12)

25

^o

C 50

^o

C 75

^o

C 100

^o

C

Frenkel-Pookle emission

Fig. 2.18 Conduction mechanism for substrate current fitting under inversion region (a) TEOS P.L (b) SiN P.L (c) SiN P.L with SSFI

Fig. 2.19 Band diagrams for (a) TEOS P.L (b) SiN P.L (c) SiN P.L with SSFI

CHAPTER 3

Reliability Issues of Fluorine Incorporation on the CESL strained HfO

₂

/SiON gate dielectric

3.1 Reliability Review

Reliability characteristics of the Hf-based dielectric such as hot carrier induced degradation (HCI), time dependent dielectric breakdown (TDDB), bias temperature instability (BTI) have been widely investigated with expected application of these materials in the high-k gate stack [1-5]. Threshold voltage (VTH) instability induced by charge trapping has been considered as one of the critical reliability issues in Hf-based high-k gate dielectrics, especially for the n-MOSFETs under substrate electron injection conditions (positive bias stress). On the other hand, V_TH degradation of n-MOSFET PBTI was primarily caused by charge trapping in bulk high-k rather than interfacial degradation [6]. Since the threshold voltage is directly related to the n-MOSFET’s on-off characteristics and eventually determines its output power supply voltage for its own purpose.

Hot carrier reliability is one of the major limitations for the implementation of the high-k gate dielectrics. We should consider the concurrent charging of the gate dielectric by the cold channel carriers injected into the dielectric when investigating

carriers near the drain region of the channel and cold carriers (channel electrons) which would be injected and trapped in the high-k layer during HCS condition.

On the other hand, one of main issues for high-k gate stack is the charge trapping characteristics during reliability test, a threshold voltage instability associated with electron trapping/de-trapping in high-k layer [10-15] can significantly affect the transistor parameters and complicate the evaluation of the effects of stress-induced defect generation phenomenon on the high-k gate stacks. It is typically not an issue in the case of SiO2 dielectrics because the reversible electron trapping is less prevalent in SiO2 and could not significantly affect transistor parameters [16-17]. We can evaluate additional electron trapping effects on top of defect generation by a de-trapping step which has been proposed for studying generation of the electron trapping process and its impact on high-k device reliability [13-14]. As a result, in the Hf-based high-k gate dielectrics, these reversible charge trapping and de-trapping behaviors are highly related to the stress history of previously trapped charge carriers, implying these high-k traps are pre-existing bulk traps [18-19]. For further understanding as mentioned above, we will investigate trapping dynamics of carrier in HfO₂ high-k dielectric n-MOSFETs.

In this chapter, we investigate the characteristics of threshold voltage (V_TH) shift during CVS and HCS to find a way to differentiate the contribution of cold carrier

trapping and hot carrier injection.

3.2 Reliability Impact of Fluorine Incorporation on CVS 3.2.1 CVS Measurement Setup

In constant voltage stress (CVS) reliability measurements, devices were stressed with the gate voltage set at a higher positive voltage, and the source/drain/substrate are ground. To monitor the degradation, both the ID-VGS characteristics at VDS = 100

mV (linear region) was measured before and after the stress. As shown in Fig. 3.1.

The degradations in terms of threshold voltage shift (∆VTH) was examined and

recorded in the accelerated stress test.

3.2.2 Result and Discussions

First of all, we focus on reliability characteristics of HfO₂/SiON gate stack nMOSFETs with fluorinated CESL compared to without fluorinated CESL and without CESL under constant voltage stress (CVS) condition. Fig. 3.2 shows the threshold voltage variations as a function of stress time for the fluorinated CESL device, CESL device and control TEOS devices of nMOSFETs, respectively. The given normalized stress was V_G-V_TH=3.0V at room temperature. In order to exclude the difference of in the threshold voltage between samples, normalized positive stress

control devices is the most serious and Vth shift of CESL is less than the former. As previous metioned, precursor of SiN sample is NH3, nitrogen atoms could passivate bulk traps. The fluorinated CESL device shows the best reduced Vth degradation compared to the both devices because effect of fluorine passivation is better than nitrogen passivation. The high-k bulk traps (NB) are an important factor of stress-induced degradation. To prove this degradation, the normalized gate current density during Fowler-Nordheim (FN) stress at VGS=4V is plotted versus stress time for all splits shown in Fig. 3.3. As observed, the normalized gate leakage current density decreases with stress time for these samples, whereas the control devices shows a higher rate of Jg decrease than the strained devices with and without fluorinatrd. And the strained devices with SSFI have the least reduction. It is consistent of previous experimental. This result indicates that there are more high-k defect traps in the high-k bulk of the control devices, causing a higher number of electrons trapped and the strained device followed. Therefore, fluorine incorporation could significantly decrease oxide bulk traps.

3.3 Reliability Impact of Fluorine Incorporation on HCS 3.3.1 HCS Measurement Setup

In hot carrier stress (HCS) reliability measurements, devices were stressed with

the drain voltage set at a highly positive voltage, and the gate terminal was biased at the voltage where maximum absolute value of ISUB occurred to accelerate the degradation. To find the condition, we first measured the ISUB-VGS characteristics with drain terminal biased at a given voltage. To monitor the hot electron degradation, both the ID-VGS characteristics at VDS = 100 mV (linear region) was measured before and

after the stress. As shown in Fig. 3.4. The degradations in terms of threshold voltage shift (∆VTH), was examined and recorded in the accelerated stress test.

3.3.2 Result and Discussions

Substrate current is an important factor to determine how much hot carriers are generated and injected during hot carrier stress. A hot carrier with sufficient energy can create more charge carriers through impact ionization. For n-MOSFET devices, holes generated by impact ionization are collected into the substrate. The substrate current (I_SUB) versus gate voltage (V_G) for these samples of devices at V_DS =3V is illustrated in Fig. 3.5. From the figure, it clearly exhibits that the fluorinated and the CESL device has larger substrate current than the control TEOS device. Because strain effect can enhance mobility and election velocity, resulting increase accelerated electron energy, they can get more hot holes. When testing hot carrier stress, the control device should have less degradation than the others. The threshold voltage shift increase as a function of stress time for these samples is shown in Fig. 3.6, after

receiving a hot-carrier stress at VGS at the maximum value of substrate current. As expected, the control sample has the least VTH shift among these samples. The fluorinated CESL samples have less threshold voltage shift than the strained samples but both samples have similar substrate current. It means that although the CESL strained with and without fluorinated generate similar amount of hot-carriers, the fluorinated samples can significantly reduce VTH shift. It indicates that the CESL device is relatively easy to be damaged by hot carrier stress. The result suggests that this phenomenon is closely related to the incorporation of fluorine atoms forming stronger Si–F bonds near the source and drain sides instead of weaker Si–H and Si–Si bonds to enhance the interface hardness between HfO2/SiON and silicon as well as the immunity against hot-carrier stress due to the inhibition of the channel avalanche multiplication of hot carriers. This mechanism could be expressed in Fig. 3.7

3.4 The Characteristics of Charge De-trapping

The threshold voltage was shifted to positive direction due to negative charges built up within the HfO2 shown in Fig. 3.2.As shown in Fig. 3.8 shows the threshold voltage shift of the HfO2/SiON gate stack nMOSFETs with fluorinated CESL, the CESL device and the control device as a function of the static stress/relaxation time with a fixed stress voltage VG-VTH=2V and relaxation voltage VG=-2V. Basically, the

relaxation voltage plays a significant role to clean up the trapped charge carriers before the next stress cycle. It was also indicated that a charge de-trapping behavior can not cause an additional VTH instability because the threshold voltage was still shifted above the initial VTH for these samples. After relaxation, a subsequent stress-induced VTH increase follows the initial pre-relaxation stress time dependence.

It is clear that this relaxation does not fully recover the VTH shift caused by the positive bias stress. The residual VTH shift appears to be determined by the balance between the built-in potential due to trapped charges and the barrier height for de-trapping [20].

Based on the observations above, a model explaining VTH instability behavior during the stress and relaxation can be proposed as shown in Fig. 3.8. There are two factors to shift V_TH during the stress. One is electrons filling the existing traps and the other is the charged damages created during the stress. Portion of the former electrons was de-trapped spontaneously to reduce the instant built-in potential after the stress was removed. However there are still some amount of trapped electrons and charged damage remaining. We can observe that a lot of trapped electron is significant to be instantly pulled out from the pre-existing traps and the created traps are also obviously decreased for the SSFI devices during de-trapping bias, resulting in a few of the residual electrons

This result could explain for two portions. For stress behavior, there are two factors to shift VTH during the stress. One is electrons filling the pre-existing traps and the other is the charged damages created traps during the stress. The fluorinated device defect level is the deepest and Hf-F bonding is the stronger than others, so electron filling the pre-existing traps and created traps which charge damage could be the least, respectively. Therefore, the fluorinated device is the least shift. Although the CESL device defect level is similar to the fluorinated, its oxide has much more Hf-H

This result could explain for two portions. For stress behavior, there are two factors to shift VTH during the stress. One is electrons filling the pre-existing traps and the other is the charged damages created traps during the stress. The fluorinated device defect level is the deepest and Hf-F bonding is the stronger than others, so electron filling the pre-existing traps and created traps which charge damage could be the least, respectively. Therefore, the fluorinated device is the least shift. Although the CESL device defect level is similar to the fluorinated, its oxide has much more Hf-H

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