Chapter 2 Device Fabrication and Measurement
2.2 Electrical characterization and measurement setup
Electrical characterizations were performed using an HP 4156 system. In all measurements, temperature-regulated hot chucks were used to control the temperatures.
In this study, threshold voltage (Vth) was calculated by the linear extrapolation method [42]. Specifically, the threshold voltage was determined from the extrapolated gate voltage VGi by
2
D
T Gi
V = V − V
(2-1)where VGi was determined by the following steps: first, the point on the ID-VG curve corresponding to the maximum in the transconductance (gm) was determined. Next, a straight line across the point was used to extrapolate the ID-VG curve and locate the intercept at the VG axis. In this work, VD was set at 0.5V.
Finally, subthreshold swing (SS) could be calculated from the subthreshold current
increase in the weak inversion region by
(log )
G D
SS V
I
= ∂
∂ (2-3)
Chapter 3
Leakage current reduction in NW-TFTs
3.1 Leakage mechanisms
According to the structure of the fabricated devices, there are two regions where leakage currents are likely to generate, i.e., the channel near the drain and the gate-to-drain overlap region. In this chapter we first briefly review possible mechanisms in these regions.
3.1.1 Leakage mechanisms in channel region
In poly-Si channels, the band diagram is modulated by the drain and gate biases.
According to the strength of the electric field at the drain/channel junction, there are basically three conduction mechanisms illustrated in Figs. 3-1(a), (b), and (c).
(a) At a low drain field, the dominant leakage current mechanism is thermionic emission.
This is due to thermal excitation of an electron from valence band into trap-state, and the trapped electron is emitted into conduction band by the same way.
(b) As the drain bias increases, the dominant leakage current mechanism is thermionic field emission. This case comprises two steps: the first step is the thermal activation of an electron from the valence band to a trap state, and the second step is electron
tunneling through the reduced barrier to the conduction band as shown in Fig. 3-1(b).
(c) Under a strong electric field, the band gap is pulled more seriously. As a result band-to-band tunneling becomes the dominant leakage current mechanism. It causes the electrons to tunnel from valence band to conductance band via the traps. .
According to Fig. 3-1 and the above discussions, these mechanisms all belong to trap-assisted leakage mechanisms. Hence the trap state density in the band gap plays an important role in the mechanism. The band-to-band current is strongly dependent on the applied bias. The pure thermal emission current is proportional to the intrinsic carrier concentration of silicon (ni), and ni is proportional to exp [-Eg/2kT] (where Eg is the energy band gap of silicon, k is the Boltzmann constant, and T is the temperature in Kelvin). For this reason, the activation energy of the pure thermal emission current should be approximately equal to Eg/2. In addition, the pure thermal generation current is nearly independent of gate voltage.
3.1.2 Leakage current mechanism in gate-to-drain overlap region
Another possible leakage current component occurring in the gate-to-drain overlap region is the gate induced drain leakage (GIDL). When the gate is negatively biased with respective to the drain and the voltage difference between the two is high, the n-type drain region overlapping the gate can be depleted and even inverted. As shown in Fig. 3-2, when the potential difference between gate and drain (VGD) increases, the energy band is pulled severely. This results in some high-field effects in the depletion region such as
avalanche multiplication, band-to-band tunneling and trap-assisted band-to-band tunneling. Hence a lot of extra minority carriers are generated and swept to the source to complete the path for GIDL.
There are many parameters that influence GIDL. VGD and the oxide thickness between gate and drain are the two most important parameters in the GIDL mechanism because they directly govern the electric field in the depletion region. Another important parameter is the volume in which minority carriers are generated. In this regard, the gate-to-drain overlap area and the drain doping concentration are the two major factors.
The drain doping concentration determines the depletion width in the gate-to-drain region.
An increasing drain doping concentration leads to a decreasing depletion width, therefore the volume in which minority carriers are generated decreases. Besides, defects that cause necessary trap sites for assisting the leakage flow also play an important role in GIDL mechanism.
3.2 Effects of Si
3N
4hard mask layer
Figure 3-3 illustrates the gate-to-drain overlap region in the fabricated device. As has been identified in previous work [43], this unique feature in the proposed device structure actually contributes to the observed GIDL current. To reduce the GIDL, an extra Si3N4 layer (HM) between gate and drain is added in this study to reduce the strength of the electric field. Reduction of the electric field could help suppress the leakage, as mentioned in Section 3.1.2.
Fig. 3-4 shows the transfer characteristics of NW TFTs with Si3N4 HM.It can be
seen that with the 3hr NH3 plasma hydrogenation treatment, the electrical characteristics of NW TFT with Si3N4 HM shows dramatic improvement as compared with the fresh device. On-current, subthreshold swing and leakage current are all improved by the NH3
plasma hydrogenation. To clarify the exact region where the leakage current occurs, the drain current (measured at maximum |VGD|) of the devices with various gate-to-drain overlap areas are compared. Such analysis is helpful to understand the impact of the gate-to-drain overlap area, which is proportional to the width of the gate electrode as is evidenced by the top view of the device shown in Fig. 3-3, on the off-state leakage. The results are shown in Fig. 3-5. In this figure it is found that the off-state leakage currents for the devices with HM are nearly identical for devices with various gate-to-drain overlap areas. Fig. 3-6(a) shows the drain current (measured at maximum |VGD|) as a function of the gate width for NW TFTs with and without the Si3N4 HM, and the drain current values normalized to that with minimum gate width (0.8 micron) are shown in Fig.
3-6(b). It can be seen that the drain current of NW TFTs with Si3N4 HM is almost independent of the gate width. In contrast, the leakage current of NW TFTs without Si3N4
HM is strongly dependent on the gate-to-drain overlap area. From these results, we can infer that the leakage current of NW TFTs without Si3N4 HM mainly occurs in the region where the gate overlaps the drain, while the leakage current of NW TFTs with Si3N4 HM mainly occurs in poly-Si nanowire channel.
We also extract the activation energy of devices to gain a deeper insight into the leakage mechanism. The activation energy is extracted using the following relation:
energy.
The equation also can be expressed as
ln(
off) ln( ) (
0E
a)
I I
kT
= + −
(3-2)The drain current data measured at 25, 50, 75, 100, and 125 ℃ are exhibited in Fig. 3-7.
Next, we use equation (3-2) to extract the activation energy. The extracted activation energies are summarized in Fig. 3-8. It can be seen that the activation energy of off-state leakage for NW TFTs without Si3N4 HM shows a stronger dependence on the gate voltage. The activation energy gradually decreases as the gate voltage becomes more negative. In contrast, the activation energy of off-state leakage for NW TFTs with Si3N4
HM is nearly independent of the gate voltage, indicating that its dependence on the strength of electric field is also weak. In other words, GIDL is greatly suppressed in these devices because Si3N4 HM can effectively shield the electrical field in the gate-to-drain overlap region. Fig. 3-9 shows the band diagram in the gate-to-drain overlap region for NW-TFTs with Si3N4 HM. Strength of electrical field at the Si/oxide interface in the gate-to-drain overlap region is dramatically reduced due to the appearance of the Si3N4 HM. It is worth noting that even though the presence of Si3N4 HM effectively eliminates the GIDL, the leakage current is still significant. A plausible reason is that the profile of poly-Si nanowire channel may have been changed in devices with an extra Si3N4 HM layer. Fig. 3-10 exhibits the cross-sectional picture of a device with HM. It is evidently seen that the poly-Si nanowire channel has a larger conduction width than the device without HM.
3.3 Effects of NH
3plasma hydrogenation
For operation of poly-Si TFTs, the conduction carriers in the channel have to overcome the barrier at the grain boundaries, the on-currents of the devices are dependent on the amount of defects contained [44]. In addition, the trap density is related to the leakage current as mentioned in Section 3.1. Therefore reducing trap density is a direct method to enhance the performance of TFTs. In this regard, hydrogenation is the most commonly used method to reduce the trap density in TFTs. It has been widely demonstrated that such approach could effectively passivate the dangling bonds at the grain boundaries as well as the intragrain strained bonds with hydrogen species.
Hydrogenation incorporation can be carried out by some different techniques, such as hydrogen plasma [45], H+ implantation [46], hydrogen-rich Si3N4 capping layer [47]
and NH3 plasma [48]. In this work, we adopt the NH3 plasma treatment to achieve the purpose. Fig. 3-11 presents the transfer characteristics of NW-TFTs with HM and subjecting to various NH3 plasma times. Detailed data are summarized in Table 3-1. After a 2hr NH3 plasma treatment, the device performance is apparently better than that of the as-fabricated counterpart. Higher mobility, higher On/Off ratio and lower subthreshold swing are observed after the plasma treatment, verifying the effectiveness of the NH3
plasma treatment.
3.4 Effects of RTA
Besides HM approach, a post-crystallization rapid thermal annealing (RTA) process
was also explored to reduce the leakage current of NW TFTs. ID-VG characteristics of devices with RTA are shown in Fig. 3-11. The NW-TFT with RTA obviously has better performance. This is believed to be due to the fact that the RTA process improves the grain quality and thus reduces the defect density. Fig. 3-12 shows ID-VG characteristics of devices with or without RTA treatment, all receiving an additional 2hr NH3 plasma hydrogenation. NW-TFT with RTA still exhibits lower leakage current after plasma hydrogenation. Similarly, we have also measured the drain current of the control devices (i.e., w/o Si3N4 hard mask) with various gate-to-drain overlap areas to analyze their leakage mechanisms. These results are shown in Fig. 3-13 and Fig.3-14. As can be seen in these figures, although the off-state current of the NW TFTs with RTA is lower than that of their non-RTA counterparts, the dependence on the gate-to-drain overlap area is still evident. This phenomenon indicates that the gate-to-drain overlap zone is the region where the leakage current originates. The extracted activation energy is shown in Fig.
3-15 for NW-TFTs. The activation energy for NW-TFTs with RTA is significantly higher than the case without RTA treatment, albeit both are influenced by the gate voltage under off-state. It is suggested that although the leakage current is reduced, the GIDL remains the major mechanism in NW-TFT with RTA.
Chapter 4
NW-TFTs fabricated by MILC
4.1 Electrical characteristics of NW-TFTs fabricated by MILC
The device structure is shown in Fig. 4.1. It was fabricated with similar process sequence as described in Chapter 2, except for the different treatments used for enhancing the film crystallization. The major steps are stated below: Briefly, after deposition of a 100nm-thick amorphous Si (a-Si) layer and subsequent S/D doping and patterning step, a 100nm-thick low-temperature oxide (LTO) was deposited by a plasma-enhanced (PE) CVD. For MILC purpose, the seeding windows were opened in the LTO layer. After opening the seeding windows, a 5nm-thick Ni layer was deposited to serve as the seeding layer. The lateral crystallization was carried out at 550℃ for 16 hours in N2 ambient. The arrows illustrated in Fig. 4-1 depict the crystallization paths. Fig. 4-2 exhibits the plane-view TEM of MILC NW-TFT. The NW channel is evidently laterally crystallized with large grain size, as shown in Fig. 4-2.
The transfer characteristics of n-type NW-TFTs fabricated by MILC are shown in Fig. 4-3. Detail electrical characteristics of devices are summarized in Table 4-1. The performance of the MILC device is obviously much better than that of the SPC device.
The extracted field-effect mobility is 247 cm2/V-sec for the MILC device, which is one order of magnitude higher than 25 cm2/V-sec of the SPC counterpart. The SS of MILC
device is about 0.25 V/dec, much lower than that of the SPC counterpart (about 0.96 V/dec). The performance s is improved by the incorporation of an additional RTA process for both MILC and SPC devices. The MILC NW-TFTs still depict better electrical characteristics including higher mobility, lower Vth, and lower SS as shown in Fig.4-4 and Table 4-1. The poly-Si channels in MILC devices have larger grains and less grain boundaries that are transverse to the current flow than the SPC devices because of lateral crystallization. The number and height of barrier at grain boundaries which conduction carriers in channel must overcome are reduced so that the MILC NW-TFTs have better conduction behavior. Fig.4-5 and Table 4-1 compare the electrical characteristics between p-type NW-TFTs fabricated by either MILC or SPC scheme. Similar to n-type devices, the p-type MILC devices have much better performance than their SPC counterparts.
Though the aforementioned enhancement in device performance is magnificent, the off-state leakage of the devices remains high despite the MILC treatment. This is likely to be due to potential Ni contamination. The formation of silicide at the grain boundaries during the MILC process has been reported previously [49], which would aggravate the leakage. This drawback could be alleviated by adopting the long Ni-offset structure [50]
or by proper annealing condition [49].
4.2 Analysis for NW-TFTs with different MILC seeding window arrangement
The location of MILC seeding window is very important because it can directly influence the electrical characteristics of devices. In this study, we exploit three splits of
samples as illustrated in Fig. 4-6 to address this issue. The splits are divided into two categories, namely, asymmetric and symmetric arrangements. In the symmetric case, two seeding windows are separately located at source and drain, while in the asymmetric case only one seeding window is situated at either source or drain.
Fig. 4-7 and Fig. 4-8 show the ID-VG characteristics of devices with asymmetric seeding window at source and at drain, respectively. The data can be analyzed by dividing them into three regions. Since the poly-Si NW channels in all devices are the same, the properties are nearly identical in the on-region. In the off-region, the leakage current in the device with seeding window at drain is higher than that with seeding window at source. This is due to the fact that the MIC region is just situated at the gate-to-drain overlap region. The Ni concentration is higher in MIC region than MILC region, and there are many grain boundaries existing at the boundary between MIC region and MILC region. The Ni-related species that accumulate at the grain boundaries or inside the grains would cause a higher trap density in the gate-to-drain overlap region, and the leakage current of the device with seeding window at drain is therefore higher. In the subthreshold region, the currents are nearly identical at VD=0.5V but the current in NW-TFT with seeding window at drain is higher than the other at VD=3V. A plausible reason is that the Ni concentration is higher near the seeding window. For the device with seeding window at drain, the Ni may produce more deep states near the drain edge. These deep states may not be active at low field (i.e. VD=0.5V) but will serve as the trap sites for trap-assisted tunneling current occurring at high field (i.e. VD=3V). As a result, the subthreshold current becomes higher when the drain bias becomes larger.
The comparison of ID-VG characteristics between devices with asymmetric and
symmetric seeding window is presented in Fig. 4-9. It is found that the device with asymmetric window at source has higher on-current and lower SS. The NW-TFTs with symmetric window have higher leakage current than NW-TFTs with asymmetric window at source. Note that in the MILC process, the crystallization proceeds radially from the seeding window. In the symmetric case, the fronts of crystallization from the opposite sides meet each other at the central region of the channel. Trace amount of metallic species may be left inside the channel, leading to the degraded on-state performance as compared with the asymmetric case.
Chapter 5 Conclusions
In this work, two methods were proposed to reduce the off-state leakage in the newly-proposed NW-TFTs. The addition of an extra Si3N4 HM layer between the gate and drain is found to effectively eliminate the GIDL occurring in the gate-to-drain overlap region, albeit the etched profile of poly-Si nanowire may need to be readjusted for optimization of the electrical characteristics. Finally, an additional RTA process is also found to effectively reduce the leakage current through the improvement of the thin-film quality, although GIDL still acts as the major leakage mechanism in the fabricated devices .
We have also employed the MILC method to improve the device characteristics.
Film crystallinity of the NW fabricated by this method is shown to be dramatically improved. Needle-like larger grain structure with crystallization direction along the NW channel is demonstrated. This leads to a single-crystal-like structure and the device characteristics could be significantly improved in terms of extremely high carrier mobility (>200 cm2/V-sec) and steeper subthreshold swing. Nevertheless, the Ni contamination would cause leakage problem in our MILC devices. More efforts are needed to address this issue.
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