Electronic control system

As shown in Figure 6.4, the control system is built on the programmable embedded controller (sbRIO-9632, National Instrument), which includes a 400 MHz real-time processor (MPC5200), and a 2M gates FPGA (Xilinx Spartan-3). The FPGA with a 40 MHz internal clock provides high speed operations. However, the limited algorithmic functions and the number of gates restrict the achievable functions in FPGA. Therefore, the functions such as the lock-in amplifier algorithm and the Z-axis feedback control are implemented by the FPGA, because the operational speed is required. On the other hand, large and complicated functions such as data access, image processes, and the user interface are accomplished in the PC. The real-time processor provides a stable speed

control, force curve measurement, and automatic tip-sample approaching.

(a) Design concept of functional assignment

(b) Photograph

Figure 6.4 Programmable embedded controller

For realizing the lock-in amplifier, the bandwidth is first considered. A typical resonant frequency for the tapping mode AFM is about 300 kHz. However, the sampling frequency of the built-in analog input/output (AIO) in the embedded controller is only around 100 kHz. Therefore, the additional high speed ADC and DAC are connected with the digital input/output (DIO) to achieve 5 MHz sampling rate. Except the sampling rate, the loop rate of the algorithm should be also considered. Although the internal clock in the FPGA is 40 MHz, executing a sequential operation requires a lot of clock periods as illustrated in Figure 6.5(a). To obtain a loop rate of 5 MHz, the pipeline

processing is adopted as shown in Figure 6.5(b). Operations are parallel executed. Each output of an operation is stored in a register, and transferred to the next operation in the next loop. The pipeline method can increase the loop rate significantly. However, the operations should be assigned properly to avoid latency increasing.

(a) Sequential processing

(b) Pipeline processing

Figure 6.5 Processing strategies of lock-in amplifier

Figure 6.6 shows the configuration of the lock-in amplifier. The whole algorithm is divided into two loops. In the main loop, the process includes three stages. The sine and cosine signals are generated in the first stage, and recorded in the register 1. At the second stage, the sine signal is multiplied by an amplitude gain to adjust its amplitude.

Next, the sine signal is transmitted to the DAC through the digital outputs, and the analog output from the DAC connects with the piezoelectric actuators to excite the

Then, the UFES is multiplied by the sine and cosine signals individually, and the results are recorded in the register 2. At the third stage, the rectangular coordinates X and Y are generated through two low pass filters (LPF). The infinite impulse response (IIR) filter is adopted, and its transfer function H(z) in z-domain is described by



 



 − −

=

1 −1

1 ) 1 (

N z N N

z

H , (6.1)

where N is an integer that is adjustable for changing the bandwidth. In the secondary loop, the rectangular coordinates X and Y are transformed into the polar coordinates amplitude R and phase θ through a built-in function in LabVIEW with a throughput of 18 cycles/sample. The secondary loop also provides the 5 MHz clock signal to both the ADC and DAC.

Figure 6.6 Configuration of lock-in amplifier

The Z-axis feedback control loop is illustrated in Figure 6.7. In the tapping mode, the amplitude R is chosen as the reference signal for the feedback control. For other modes, the external reference signal can be acquired through the analog input (AI). The error signal is calculated by the reference minus the setpoint, which is the tracking target set by user. The proportional-integral (PI) controller is utilized to compensate the Z-axis output signal Zout. In the proportional controller, the error is multiplied by the P-gain simply. In the integral controller, the error is multiplied by the P-gain, and is accumulated for eliminating the steady state error. The error accumulation will be paused for avoiding overflow if the Zout reaches the maximum/minimum value. The Zout

is the summation of the outputs from the proportional and integral controllers. When the feedback control is switched off, the Zout is set to a constant defined by user.

Figure 6.7 Z-axis feedback control configuration

Figure 6.8 shows the scanning control procedure. The scanner is set to the initial position in the beginning. After the Z-axis feedback is switched on, and the line scan is executed. The data such as the height, the amplitude, and the phase are transmitted to the PC after finishing one line scan. Then, the scanner moves to the initial position of the next line, and repeats the line scan until completing the final line.

Figure 6.8 Scanning control flowchart

The raster scan method is utilized for scanning, and the scan area can be rotated arbitrarily. To set the scanner initial position with a rotational angle θr, the calculation is illustrated in Figure 6.9. The largest black square represents the full scan range of the scanner. The blue square with dashed line is the scan range without the rotation, and its initial coordinates are denoted by (x, y). First, the offset of (x, y) is subtracted, and the shifted coordinates (xo, yo) become

Figure 6.9 Scheme of coordinate rotational of scan range

During the line scan, triangular waveforms are used to control the X-axis and Y-axis displacement, and their amplitudes depend on the scan range and the rotational angle θr. However, as the black line in Figure 6.10(a), the driving signal (XRT, YRT) in the digital real-time processor is not perfect triangular. If the displacement on each step is too large, this driving signal could cause an oscillatory step response of the scanner. For avoiding this problem, a slew rate limitation is accomplished by the FPGA, and the blue line represents the final driving signal (Xout, Yout). Figure 6.10(b) and 6.10(c) show the flowcharts in the real-time processor and the FPGA, respectively. Each line scan can be divided into the forward and backward trajectories. In the forward trajectory, the displacement (Δx, Δy) of one step is added to (XRT, YRT) step by step until the end of the trajectory. In the backward trajectory, the same displacement (Δx, Δy) is subtracted from (XRT, YRT) until the initial position. During the scanning, the slew rate limiter in Figure

(YRT). Reversely, Xout (Yout) is decreased when XRT (YRT) is smaller than Xout (Yout). The slew rate is adjustable through changing the loop rate.

(a) Driving signal for scanning

(b) Line scan flowchart in real-time processor (c) Slew rate limiter in FPGA Figure 6.10 XY-axes scanning control process

The tip-sample approaching process is illustrated in Figure 6.11, and the continuous approaching method is adopted. At first, the Z-axis feedback control is switched on, and the setpoint must be set properly. After the Zout reaches the maximum

value, the motor starts to move the sample toward the tip. The Zout is monitored continuously, and it will decrease when the tip contacts with the sample surface. When the Zout is less than the half of the full range, the motor is stopped to finish the approaching. At first, the motor speed is tuned for avoiding tip damage. The approaching speed of about 450 nm/sec (50 steps/sec) is chosen, and no overshooting on the UFES can be observed in this case. For decreasing time consumption, the motor can be controlled manually to bring the sample closer to the tip.

Figure 6.11 Tip-sample approaching process