De-embedding Theory

When circuits or devices work at high frequencies, many parasitic effects will happen. For example, a signal applied on one metal line, the potential of this metal line at any point is equal if the wavelength of signal is long enough, compared with the metal

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line. However, the potential of the metal line at any point will be different when the wavelength of signal can compare with the metal line or shorter, i.e. high frequency signal. Hence, at low frequency, a metal line was regarded as a resistor. On the other hand, a metal line was regarded as resistor plus parasitic inductance and capacitance parameters at high frequency in an equivalent circuit model.

In order to measure this MIM capacitance, we must layout additional pads and signal lines for measurement. However, these added potions will generate additional parasitic effects. So we must de-embed these parasitic parameters to get the intrinsic high frequency capacitance.

As devices were measured approach microwave frequency, we cannot directly measure the lump circuit components, like RLC (resistance, inductance, and capacitance), because of parasitic effects. Scattering-parameters (S-parameters) were obtained in general [63]. According to microwave theorem [63], we can transform the S-parameters into an equivalent circuit model to extract the component that we want.

Among added portions for measurement, the parasitic capacitance effects dominate in probe pads. We can transform both of the measured S-parameters of MIM capacitors and “OPEN” dummy device into admittance parameters (Y-parameters). Then we de-embed the parasitic capacitance effects from the MIM capacitor by YMIM-YOPEN. So, we can obtain the de-embedded S-parameters from the transformation of

de-embedded Y-parameters (the simulated S-parameters shown in Figure 5-4(a)). Thus, we have de-embedded the parasitic capacitance effects due to the probe pads of MIM capacitor.

Then, we use an equivalent circuit method to simulate the de-embedded S-parameter to extract each components of the equivalent circuit model shown in Figure 5-4(b). From this, we can obtain the RF capacitance of MIM capacitor.

The capacitance values were measured directly using LCR meter from 10 KHz to 1 MHz and calculated from the de-embedded S-parameters up to 20 GHz using the following equation [14]: We can use the equation (5.1) to derive the capacitance densities at different frequencies:

Z(C) in equation (5.2) is the total impedance in the equivalent circuit model of Figure 5-4(b) and Z0 is the characteristic impedance of transmission line. The RF frequency in equation (5.1) is obtained by differentiating the measured S21 in equation (5.3), where shows the relation between the S21 and total impedance Z(C). Figure 5-5(a) shows that the derived decreases rapidly with the increasing frequency, which is advantageous for high frequency analog/RF circuits.

/ ΔC C

/ ΔC C

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5.4 Results and discussion

A. C-V ,I-V,ΔC/C, and TCC characteristics

Figure 5-1 shows the C-V characteristics for TaN/STO/TaN MIM capacitors. A very high capacitance density of 35 fF/μm² or 0.99 nm capacitance-equivalent-thickness (CET) is measured at 1 MHz. Such high capacitance density provides a 35 times area reduction than the ~1 fF/μm² value provided by foundry [55]. In addition, a near constant capacitance value with little voltage and frequency dependence is obtained for the STO MIM capacitor, which is important for RF IC under large voltage swing condition. Such high capacitance density is due to the very high κ value of 169 in STO dielectric that is significantly larger than the κ~20 of HfO2 used in current DRAM manufacture and also higher than the κ~45 in TaTiO MIM capacitors [21], [60]. Since the STO is also shown in the future DRAM technology roadmap [59], it is highly possible to integrate the RF capacitor with DRAM for multi-functional SoC application.

Figure 5-2 shows the J-V characteristics ofSTO MIM capacitors. Small leakage current of only 1×10^-7 A/cm² (7×10^-7 A/cm²) is obtained at 1V (2V) with high capacitance density of 35 fF/μm². The small leakage current under positive bias voltage (electron injection from bottom electrode) indicates the good bottom STO/TaN interface, where the higher leakage current under negative bias is attributed to the surface roughness originated from STO crystallization. However, such crystallization is needed

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for STO to give a much higher κ value than amorphous HfO2 and TaTiO. For a typical large 1 pF capacitor used in RF IC, a very small leakage current of only 29 fA is obtained due to the very high κ value, which is much smaller than the off-state current of a MOSFET with deep sub-100nm gate length [61]-[62].

For analog capacitors a low capacitance voltage linearity is important. Figure 5-3(a) shows a ΔC/C-V plot for TaN /STO/TaN MIM capacitors with 35 fF/μm² density. We obtained quadratic voltage linearity (α) of 542 ppm/V² for the capacitance. Figure 5-3(b) shows the temperature dependence of normalized capacitance of STO MIM capacitor.

The TCC showed an increase trend with increasing measured temperature.

B. High frequencies characteristics

Figure 5-4(a) shows the measured S-parameters for the 35 fF/μm² density TaN/STO/TaN capacitors. The capacitance values at RF frequency were extracted using the equivalent circuit model in Figure 5-4(b): the MIM capacitor is modeled by Rp and C, where the Rp originates from the high-κ dielectric loss. In addition, the Rs, Ls1, and Ls2

represent the parasitic impedances in the coplanar transmission line used for RF measurements. Good agreement between measured and simulated data are obtained over entire frequency range from 200 MHz to 10 GHz indicating the equivalent circuit model suitable and reliable for the TaN/STO/TaN modeling and capacitance value extraction.

Figure 5-5(a) shows the dependence of capacitance density as a function of

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frequency, where the data at RF frequency region is extracted from the circuit model with well matched S-parameters and the data at intermediate frequency (IF) are obtained from the measured C-V characteristics. A small capacitance reduction of only 4.1% from 100 kHz to 10 GHz is obtained indicating the good quality of device performance over the IF to RF range [21], [60]. However, such extracted capacitance density at RF regime is not sensitive enough to calculate the small ΔC/C variation- important for precision capacitors operated under large signal swing. We have used the previous circuit-theory-derived equation to calculate the ΔC/C-V from measured S-parameters and the results are also shown in Figure 5-5(a) and 5-5(b). The measured ΔC/C-V can be fitted with a second order polynomial equation, where linear (β) and quadratic (α) voltage coefficients of ΔC/C were obtained. Since the β effect can be canceled by circuit design using differential method, α is the key parameter to cause the unwanted

voltage-dependent ΔC/C. The obtained ΔC/C and α have been plotted in Figure 5-5(a).

Fortunately, the ΔC/C decrease with increasing frequency into RF region, which is attributed to the trapped carriers being unable to follow the high frequency signal with typical carrier lifetimes in the range ms to μs [14]-[15], [19]-[20]. The device quality (Q) factor is shown in Figure 5-6, which was extracted from measured S-parameters using a circuit model [57], [60] at RF frequencies. A capacitance value of 14 pf was obtained and consistent to the 35 fF/μm² density measured by C-V. A good Q-factor >50 is

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obtained for RF application before resonant frequency (fr) of ~13 GHz, where the relative low fr is due to the large capacitance.

The important device parameters for the analog capacitors are summarized in Table 5-1. Among the previous high-κ capacitors, the TaN/STO/TaN capacitor provides a promising and effectively solution to improve VCC-α, while maintaining very high capacitance density.

5.5 Conclusion

Very high 35 fF/μm² capacitance density, low capacitance reduction of 4% from 100 kHz to 10 GHz and small leakage of 1×10^-7 A/cm² at 1 V were simultaneously achieved in very high-κ TaN/STO/TaN MIM capacitors. This high density MIM capacitor is important for largely down-scaling the capacitance size and integration with DRAM.

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Table 5-1. Comparison of important device data for MIM capacitor with various

high-κ dielectrics.

-3 -2 -1 0 1 2 3 30

35 40

Capacitance (fF/μm2 )

Gate Voltage (V)

Area=20μmx20μm

100 kHz 500 kHz 1 MHz 0.2 GHz 2 GHz 4 GHz 6 GHz 10 GHz

Figure 5-1 The C-V characteristics of TaN/STO/TaN MIM capacitors. Very high capacitance density of 35 fF/μm² is measured at 1 MHz with small capacitance variation. The C-V results from 100 kHz to 1 MHz are measured from LCR meter and the data from 0.2 GHz to 10 GHz are obtained from the S-parameters.

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-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 10^-8

10^-6 10^-4 10^-2 10⁰

35 fF/μm² capacitance density

Current density

(

A/cm2

)

Voltage(V)

Top injection Bottom injection

Figure 5-2 The measured J-V characteristics of TaN/STO/TaN MIM capacitors with large 35 fF/μm² density.

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-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

Figure 5-3 (a) ΔC/C-V plot for TaN /STO/TaN MIM capacitors (b) Temperature-dependent normalized capacitance for TaN /STO/TaN MIM capacitors.

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0.5 1.0 2.0 5.0

Figure 5-4 (a) The measured and simulated two-port S-parameters for STO MIM capacitors, from 200 MHZ to 10 GHz. (b) The equivalent circuit

for capacitor value extraction from measured S-parameters.

model

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100k 1M 10M 100M 1G 10G

10

¹

Figure 5-5 (a) Frequency dependent capacitance density, ΔC/C and α for a STO MIM capacitor biased at 1.5V. The data for frequency > 1 MHz were obtained from the S-parameters. (b) The ΔC/C characteristics of a STO MIM capacitor at RF regime.

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89

0

0 5 1

0 100 200 300 400 500

Frequency (GHz)

(b)

Figure 5-6 Q-factor of TaN/STO/TaN MIM capacitors biased at 2V.

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Chapter 6

Conclusion

Using micro-crystallized high-κ SrTiO3 on NH3 treated TaN bottom electrode,a very high density of 35 fF/μm² is measured in a radio frequency (RF) metal-insulator-metal (MIM) capacitor using high-κ (κ = 169) SrTiO3. A very small capacitance reduction of 4.1% from 100 kHz to 10 GHz, low leakage current of 1×10^-7 A/cm² at 1 V is simultaneously measured. The small voltage dependence of a capacitance ΔC/C of 637 ppm is also obtained at 2 GHz, which ensures this MIM capacitor useful for high precision circuits operated at a RF regime. Although this work could achieve high capacitance density and low leakage current at the same time, but its higher PDA temperature (>450^oC) to form nano-crystal is an important issue in the back-end process flow.

Second, in order to further study the characteristics of SrTiO3, the impact of Ta2O5

doping on electrical characteristics of SrTiO3 MIM capacitors was studied for the first time. Using high-κ Ta2O5 doped STO dielectric (PDA temperature:420^oC), an absolute value of quadratic voltage coefficient of capacitance (VCC-α ) of 420 ppm/V² and high capacitance density of ~20 fF/μm² are achieved in this work. This is approximately one order of magnitude better than the same device using a pure STO, with added advantages of improved voltage and temperature coefficients of capacitance. Besides, the degradation of electrical properties after stress is all reduced, in contrast with using a pure STO. In our previous work of STO MIM, although nano-crystallized STO shows higher κ values and good device characteristics, the nano-crystallized STO requires a

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heat treatment at 450~500^oC under an oxygen ambient. This activation maximum temperature (>450^oC) cannot permit for the backend integration.

In addition, we have also developed successfully a novel plasma treatment on dielectric film to improve the electrical properties of MIM capacitors. This improvement may arise from the nitrogen atom assists to passivate oxygen vacancies in the TiNiO dielectric and eliminate the electron leakage path mediated by the oxygen vacancies.

Moreover, high 16 fF/μm² density and very low 7×10^-9 A/cm² A/cm² leakage current are all measured in novel high-κ TiPrO (κ=26) MIM capacitor with high work-function Ir, which meet well the ITRS roadmap requirement for analog IC at year 2018.

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Recommendation

The possible influences on voltage dependence of capacitance are summarized as the following section:

(A). Interfacial layer:

The interfacial layer is responsible for higher leakage current, degraded VCC and TCC, as discussed above, and which may be due to the higher trap density from the oxygen deficiency. For this reason, lower fabricated temperature or NH3 plasma treated TaN should be used to suppress interfacial layer growth from inter-diffusion and reaction between dielectric and electrode.

(B). Surface roughness:

The surface roughness could induce higher leakage and ΔC/C due to local electric field enhancement. It is interesting that the amorphous dielectric, such as TiPrO and TiNiO exhibit the bottom injection is the worse case due to poly-crystallized lower electrode. However, the crystallized material, such as SrTiO3 shows the gate injection is the worse case from degraded top interface, which is significant with increasing dielectric thickness. Consequently, using amorphous dielectric and electrode may be a good method for this concern.

(C). Dielectric thickness:

The VCC-α is strongly dependent on the capacitance density and electric field across on dielectric: an exponential decrease of α with increasing capacitance effective thickness (CET), or 1/C, was observed for all the capacitors. In other words, for the same CET or capacitance density value, the higher-κ dielectric has the lower VCC-α due to lager thickness and decreased electric field. The α−1/C dependence is important to choosing the required C density and also meeting the analog specifications of a low α.

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In conclusion, MIM capacitors incorporating a higher φm top electrode and a higher κ dielectric provide a practical approach to achieve low thermal leakage and good VCC simultaneously, without reducing the capacitance density - as in a multi-layer or laminate structure.

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