T EST C HIP I MPLEMENTATION

Fig. 4.28 Layout of present 512k Test Macro

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Fig. 4.29 Test Macro Location in Test Chip

Fig. 4-28 shows the overall layout view and Fig.4-29 shows the test chip location.

We can see that we partition the 512kb cells array into 16 banks and place it at left half of this die. Array has two power domain : 1.0V for cell array and 1.2V for control logic. The array occupies the largest part of area. Since we have to get the Vread and Vtrip separately, we implement two set of measure circuits. So total number of OPA is seven (4 for two set voltage circuit, one for voltage divider, and two for calibration) . All the OPA is locate at the middle strip of the chip with a 3.3 V power supply. Four VCO and resistor voltage divider are implemented at the right side of the chip and owns their individual power supply. The overall die area is 2555umx1333um with 27 input pin and 7 power domain.

Array Based Measurement

Other Experiments

2644um

1290um

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Chapter 5

Conclusions

For the past decades, the Moore‟s law has a good match to the CMOS technology development trend. The process has been pushed to the 20nm in the industry. Although the single core Base Band Digital system has bound to a limit due to the several issue as leakage, etc, new approach such as multi-core applicant has emerging at recent years. With network technology spread wide, new coming clouding computing is also an important issue. As a result, the high speed application has not stopped its progress. However, multi-core system and clouding system always need large amount data access process which has to assist with memories, especially SRAM. This result memory always dominant the overall speed of one system.

With the beyond 100nm technology, memory (SRAM) design suffers variation issue. SRAM no longer easy survived at novel technology due to several issue such as local random variation, leakage, etc. To allow SRAM fully functionally operation at novel technology and without loss the operation speed, or cause too much power consumption is the main stream of current SRAM design.

In this thesis we discuss two adaptive read/write ability improvement circuit techniques. As shown in simulation result, we could successfully push the read/write VCC_min, and allow this design to keep higher stability at nominal voltage operation.

Both the WLUD and DAWA are implemented in full CMOS technology that allow lesser cost. And the corner tracking ability could resist the die-to die variation that could maximize the read/write improvement. With Both implemented two circuit

96

techniques, operation speed has just slightly degraded. This means we still could keep the original operation speed.

Another part of this thesis discuss one RSNM/WM testing macro in 6T SRAM Array. To build in a large array macro could let us collect enough amount data to analyze the statistical distribution of RSNM/WM. With modified RSNM cell and proposed Vtrip and Vread measurement scheme, we could can easily to get the extremely case of read disturb and write margin. With the aid of voltage measurement scheme, all the control, In/output are fully digital. This means we could all use simple computer control without expensive measurement equipment. All the measurement could be digital automation which could save the testing time and money cost.

1

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1

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2

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3

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4

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5

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