M EASUREMENT METHODOLOGY AND CIRCUIT BLOCKS

Array Vread & ADC

V_trip N-Bit

output

Fig. 4.23 ADC Measurement Scheme

As discuss before, we have implement a 512kb modified cell array, so we can get voltage value of Vtrip and Vread from the bus of each bank. However, it is difficult to directly get precise a voltage value from the packaged chip. Traditional way to measure a chip is to directly probe the nacked die. But probe method is hard to be automation and the measurement equipment always expensive that makes the measurement cost lots of money and time. In order to save the cost, we adopt the digital measurement scheme to measure our target voltage value. Since the digital measurement scheme is used, all the input and output will be digital pin which could be automatic control and easily retrieve voltage value from digital output. One method is to implement the Analog-to-Digital-Converter (ADC) to realize the digital measurement scheme. However, ADC is quite difficult to design and ADC always

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occupies a large portion area and power in the whole system. In this work, we adopt another measurement scheme of VCO which is proposed from previous work [17][18].

We only implement the operational amplifier, VCO, and digital counter to prevent the complex design of ADC.

Fig. 4.24 VCO + Counter Based scheme

The basic idea of this measurement scheme which is proposed by [17][18] is to transform the analog voltage to frequency by VCO, and set a specific time period T to count the cycle number M. Then we divide M by T, we can get the frequency period of VCO. If we have the mapping table of frequency to input voltage, we would retrieve the measured voltage such as Vtrip and Vread by this relation without using ADC. In this work, we build two path : reference path and measurement path. Both reference path and measurement path have the same circuit component. However the difference of these two path is that the input voltage of reference path is a specific voltage from the cell in dummy column we build in each bank but the input voltage of measurement path can be the Vtrip (or Vread) of any other cell in the array. And the reference path is to provide a time base T to allow the measurement path to count the frequency cycle numbers which reflect the absolute value of Vread and Vtrip. If there exists voltage difference between two pathes, the counting number M would change and we still could get the value by mapping table. So the counting bit decides the

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Fig. 4.25 Building blocks of voltage measurement scheme

Vctrl

4-26(a) shows the circuit schematic of single stage of the VCO. We connect measured voltage to the gate of MOSFET to control the current drive ability, so that the delay of each stage will change with input voltage. However, the measured Vtrip and Vread

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always be a lower level from VDD and we hope the output frequency has higher sensitivity to control voltage, we use PMOS as the control of the delay chain. As the input voltage rise, the delay and the output frequency period increase. Fig shows the voltage to frequency plot of this VCO. We can achieve approximately 480 MHz/mV (Fig.4-27) sensitivity to this VCO implementation.

T

T₁

T₂

count = 1

count = n ^∆t

∆t

When n is large, ∆t/n can be ignored.

VCO N-bit

counter f_C

N-bit

Voltage I/O

Fig. 4.27 VCO with counter based measurement scheme concept

Every bus of each bank would be mux together before we connect it to the voltage input of VCO. In order to reduce the noise and the couple effect, we add a unit-gain buffer between them. Unit gain buffer is composed by a feedback connected

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OPA and shows in the Fig. This OPA should have larger gain to reduce the voltage difference between the input and output. And the input voltage range should prefer lower voltage level because Vtrip and Vread usually no more than 400~500mV. As for the frequency bandwidth, we don‟t have specific request. Besides, the output frequency of VCO reaches several hundred MHz, so we divide the frequency about 1000 by a 10 bit frequency divider (FD) before we connect it to counter.

We set counter of the reference path as a 13 bit counter, and the counter of measurement path is a 14 bit counter. This could allow us to have a resolution about 0.167mV to cover the voltage-frequency resolution.

For WM measurement, we realize one set of resistor voltage divider (Fig. 14) which has 64 voltage levels with 10mV of each step from 0mV to 640mV for sweeping BL level. Because the WM usually not a high value, so we choose a narrower range to increase resolution. Besides, we simply use the poly resistor to form a resistor voltage divider so that we can prevent the resistor variations. One NMOS is connected to the voltage divider as a port to access the each voltage level.

Since we have 64 voltage level, a 6 bit decoder is implemented for selection. So that we can control these 6 bit input to set BL voltage level by the outside equipment.

Furthermore the output of these resistor voltage dividers is connected to a unit-gain buffer to decouple noise. And this voltage would be directly connected to the wm_BL bus.