Evidence of Long-range Coulomb Interactions

Finally, in Figure 4.9 we quote simulated transconductance at V

_d

= 1.0 V and V

_g

of 0.75 and 1.0 V above threshold [1] versus L

m

, for comparison with measured transconductance at V

_d

= 0.8 and 1.0 V in this work. Evidently, the dimension of our devices, which is carefully chosen to meet the criterion, lies across the activation point of long-range Coulomb effects. With above evidence, we further argue that the long-range Coulomb interactions would be the main factor for performance degradation in ultra-short devices.

16

Chapter 5 Conclusion

In this work, TCAD-based inverse modeling has been carried out with aim reconstruct the process parameters. Consequently, interesting and useful results have been created. First, the overlap region for short-channel device can be accurately determined. Also the halo implant P

halo

, which has a significant impact on the substrate doping concentration and further affect the inversion layer charge density, is also solved by calculating the free electron density in the channel region from 2D simulation. Moreover, the parasitic source/drain resistance (

R

_sd ) is also extracted from the calibration model. In addition, we also provide experimental method to estimate the

R

_sd for the comprehensive analysis.

Second, the resulting temperature power-law exponent (γ) as extracted from our experimentally-determined additional mobility data points out that the long-range Coulomb interactions exist in the metallurgical channel length less than about 40 nm.

Thus, experimental evidence of long-range Coulomb interactions has been drawn.

Furthermore, underlying physical origins have all been distinguished for short channel device. Therefore, long-range Coulomb effect, which is not to be ignored in ultra-short devices, has been for the first time experimentally corroborated in the device samples under study.

17

References

[1] M. V. Fischetti , S. Jin , T.-W. Tang , P. Asbeck , Y. Taur , S. E. Laux , M. Rodwell and N. Sano, “Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model,” J. Comput. Electron., vol. 8, p.60 , 2009.

[2] M. V. Fischetti and S.E. Laux, “Long-range Coulomb interactions in small Si devices. Part Ⅰ: Performance and reliability,” J. Appl. Phys., vol. 89, no. 2, pp.

1232-1248, January 2001.

[3] K. Rim, S. Naeasimha, M. Longstreet, A. Mocuta, and J. Cai, “Low field Mobility characteristics of sub-100 nm unstrained and strained si MOSFETs,” in IEDM

Tech. Dig. , pp. 43-46, 2002.

[4] Antoine Cros, Krunoslav Romanjek, Dominique Fleury, Samuel Harrison, Robin Cerutti, Philippe Coronel, Benjamin Dumont, Arnaud Pouydebasque, Romain Wacquez, Blandine Duriez, Romain Gwoziecki, Frederic Boeuf, Hugues Brut, Gerard Ghibaudo and Thomas Skotnicki, “Unexpected mobility degradation for very short devices: A new challenge for CMOS scaling,” in IEDM Tech. Dig., pp.

663-666, 2006.

[5] Vincent Barral, Thierry Poiroux, Daniela Munteanu, Jean-Luc Autran, and Simon Deleonibus, ‘Experimental investigation on the quasi-ballistic transport: part II—backscattering coefficient extraction and link with the mobility,” IEEE Trans.

Electron Devices, vol. 56, no. 3, pp. 420-430, March. 2009.

[6] P.Packan, S.Cea, H.Deshpande, T.Ghani, M.Giles, O.Golonzka, M.Hattendorf, R.Kotlyar, K.Kuhn, A.Murthy, P.Ranade, L.Shifren, C.Weber and K.Zawadzki,

“High performance Hi-K + metal gate strain enhanced transistors on (110) Silicon,” in IEDM Tech. Dig., pp. 63-66, 2008.

[7] M. V. Fischetti, “Long-range Coulomb interactions in small Si devices Part II.

18

Effective electron mobility in thin-oxide structures,” J. Appl.Phys., vol. 89, no. 2, pp. 1232–1250, Jan. 2001.

[8] Ming-Jer Chen, Li-Ming Chang, Shin-Jiun Kuang, Chih-Wei Lee, Shang-Hsun Hsieh, Chi-An Wang, Sou-Chi Chang, and Chien-Chih Lee,

“Temperature-oriented mobility measurement and simulation to assess surface roughness in ultrathin-gate-oxide ( ~1 nm) nMOSFETs and Its TEM evidence,”

IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 949-955, April. 2012 .

[9] Schred, http://nanohub.org/resources/schred.

[10] M. J. Chen, C. C. Lee, and K. H. Cheng, “Hole effective masses as a booster of self-consistent six-band k‧p simulation in inversion layers of pMOSFETs,”

IEEE Trans. Electron Devices, vol. 58, pp. 931-937, April 2011.

[11] S. Takagi and M. Takayanagi, “Experimental evidence of inversion-layer mobility lowering in ultrathin gate oxide metal-oxide-semiconductor field-effect-transistors with direct tunneling current,” Jpn. J. Appl. Phys., vol.

41, pt. 1, no. 4B, pp. 2348-2352, Apr. 2002.

[12] TCAD. http://www.synopsys.com/Tools/TCAD/Pages/default.aspx.

[13] D.W. Lin, M. L. Cheng, S.W.Wang, C. C.Wu, and M. J. Chen, “A novel method of MOSFET series resistance extraction featuring constant mobility criteria and mobility universality,” IEEE Trans. Electron Devices, vol. 57, no. 4, pp.

890–897, Apr. 2010.

[14] K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, "Improved split C-V method for effective mobility extraction in sub-0.1-μm Si MOSFETs," IEEE

Electron Devices Letters, vol. 25, no. 8, pp. 583-585, Aug. 2004.

19

Figure 1.1 Schematic of electron transport under long-range Coulomb interactions with S/D plasmons

.

oxide

N ⁺ N ⁺

S/D plasmons

P ⁺ halo P ⁺ halo

20

Figure 1.2 Flowchart of inverse modeling in this work.

CV & IV fitting

Evidence for Long-range Coulomb Interactions

from S/D

Inverse Modeling

Doping Profile, Ninv, Rsd

Effective Mobility

Additional Mobility and Temperature Dependence

Power-Law

To Determine Main Source of Mobility Degradation for Short

Channel Device

21

0.0 0.5 1.0 1.5 2.0

-5.0x10

^-6

0.0 5.0x10

^-6

1.0x10

^-5

1.5x10

^-5

2.0x10

^-5

2.5x10

^-5

3.0x10

^-5

3.5x10

^-5

4.0x10

^-5

I _b I _g

I _d

C u rr e n t (A )

Gate Voltage (V) T=292K

T=330K T=360K T=380K

I _s

V

_d

=0.05V L _g =1  m

Figure 2.1 Temperature-dependent terminal currents at V

_d

=0.05V versus V

_g

for L

g

=1μm.

22

0.0 0.5 1.0 1.5 2.0

0.0 5.0x10

^-5

1.0x10

^-4

1.5x10

^-4

2.0x10

^-4

2.5x10

^-4

V

_d

=0.05V L _g =65nm

I _g &I _b I _s &I _d

C u rr e n t (A )

Gate Voltage (V) T=292K

T=330K T=360K T=380K

Figure 2.2 Temperature-dependent terminal currents at V

_d

=0.05V versus V

_g

for L

g

=65nm.

23

0.0 0.5 1.0 1.5 2.0

0.0 5.0x10

^-5

1.0x10

^-4

1.5x10

^-4

2.0x10

^-4

2.5x10

^-4

V

d

=0.05V L

g

=50nm

Cu rr en t ( A)

Gate Voltage (V) T=292K

T=330K T=360K T=380K

I s &I

d

I g &I

b

Figure 2.3 Temperature-dependent terminal currents at V

_d

=0.05V versus V

_g

for L

g

=50nm.

24

-3 -2 -1 0 1

0.0 0.4 0.8 1.2 1.6 2.0

C ap ac ita nc e (  F/ cm

2

)

Gate Voltage (V) Experiment

Schred [9]

Simulation [10]

W/L=10/1  m N

poly

=1e20cm

^-3

P

sub

=4e17cm

^-3

t

ox

=1.27nm

Figure 2.4 Comparison of the measured and simulated gate capacitance versus gate voltage.

25

Figure 2. 5 TEM image of the sample.

<001>

<110>

26

Figure 2.6 The schematic diagram for current flow of nMOSFETs with large gate tunneling current. Besides, I

S

<0 and I

d

>0.

27

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

L

_m

(nm) 1000 48 33 Exp

TCAD

C ha nn el C ur re nt (A )

T=292K

Gate Voltage (V)

W=1  m t

_ox

=1.27nm

N

_sde

=4.95e20cm

^-3

P

_halo

=2.5e19cm

^-3

P

_sub

=4e17cm

^-3

V

d

=1.0V

V

d

=0.05V

Figure 3.1 Measured and simulated I

_ch

versus V

_g

at T=292K and V

_d

=0.05 and 1V.

28

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

L

_m

(nm) 1000 48 33 Exp

TCAD

C ha nn el C ur re nt (A )

T=330K

Gate Voltage (V)

W=1  m t

_ox

=1.27nm

N

_sde

=4.95e20cm

^-3

P

_halo

=2.5e19cm

^-3

P

_sub

=4e17cm

^-3

V

d

=1.0V

V

d

=0.05V

Figure 3.2 Measured and simulated I

ch

versus V

g

at T=330K and V

d=

0.05 and 1V.

29

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

L

_g

(nm) 1000 65 50 Exp

TCAD

C ha nn el C ur re nt (A )

T=360K

Gate Voltage (V)

W=1m t

_ox

=1.27nm

N

_sde

=4.95e20cm

^-3

P

_halo

=2.5e19cm

^-3

P

_sub

=4e17cm

^-3

V

d

=1.0V

V

d

=0.05V

Figure 3.3 Measured and simulated I

ch

versus V

g

at T=360K and V

d

=0.05 and 1V.

30

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

L

_m

(nm) 1000 48 33 Exp

TCAD

C ha nn el C ur re nt (A )

T=380K

Gate Voltage (V)

W=1m t

_ox

=1.27nm

N

_sde

=4.95e20cm

^-3

P

_halo

=2.5e19cm

^-3

P

_sub

=4e17cm

^-3

V

d

=1.0V

V

d

=0.05V

Figure 3.4 Measured and simulated I

ch

versus V

g

at T=380K and V

d

=0.05 and 1V.

31

Figure 3.5 Calibrated 2D simulation structure for L

g

=1μm and hence L

m

=1μm. W

D

is the width of the mid-channel depletion region.

W _D

=45.53nm

P-type substrate

Depletion edge

Spac er Spac er

Drain

Silicide Silicide

Halo Halo

Con t act Con t act N ⁺ -Poly Gate

Source

Doping Conc. (cm ^-3 ) L _g =1µm

L _m ≈1µm

32

Figure 3.6 Calibrated 2D simulation structure for L

g

=65nm and hence L

m

=48nm. W

D

is the width of the mid-channel depletion region.

N ⁺ -Poly Gate

W _D = 57.27nm Depletion edge P-type substrate

Spacer Spacer

Con tact Con tact

Silicide Silicide

Source Drain

Halo

L _g =65nm

Doping Conc. (cm ^-3 )

L _m =48nm

33

Figure 3.7 Calibrated 2D simulation structure for L

g

=50nm and hence L

m

=33nm. W

D

is the width of the mid-channel depletion region.

N ⁺ -Poly Gate

W _D = 65.75nm Depletion edge P-type substrate

Spacer Space r

Con tact Con tact

Silicide Silicide

Source Drain

Halo

L _g =50nm

Doping

Conc. (cm ^-3 )

L _m =33nm

34

-5.0x10

^-7

0.0 5.0x10

^-7

1.0x10

^-6

1.5x10

^-6

2.0x10

^-6

2.5x10

^-6

0.0

5.0x10

¹⁹

1.0x10

²⁰

1.5x10

²⁰

2.0x10

²⁰

2.5x10

²⁰

L=65nm

e D e n s it y ( cm

-3

)

Y (cm) area=N

_inv

Figure 3.8 The free electron density under the surface 30nm at one position of the channel region.

35

Figure 3.9 The schematic diagram for inversion layer charge density of metallurgical length L

m

=1μ m.

36

Figure 3.10 The schematic diagram for inversion layer charge density of metallurgical length L

_m

=48nm.

37

Figure 3.11 The schematic diagram for inversion layer charge density of metallurgical length L

_m

=33nm.

38

Figure 3.12 The calculated N

inv

along the channel direction under interface 30nm for L

m

= 1μm at T= (a) 292K, (b) 330K, (c) 360K, and (d) 380K.

39

Figure 3.12 The calculated N

inv

along the channel direction under interface 30nm for L

m

= 1μm at T= (a) 292K, (b) 330K, (c) 360K, and (d) 380K.

40

-0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0

-0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0

Figure 3.13 The calculated N

inv

along the channel direction under interface 30nm for L

_m

= 48nm atT= (a) 292K, (b) 330K, (c) 360K, and (d) 380K.

41

-0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0

-0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0

Figure 3.13 The calculated N

inv

along the channel direction under interface 30nm for L

_m

= 48nm at T= (a) 292K, (b) 330K, (c) 360K, and (d) 380K.

42

-0.02 -0.01 0.00 0.01 0.02 0.03

0.0

-0.02 -0.01 0.00 0.01 0.02 0.03

0.0

Figure 3.14 The calculated N

inv

along the channel direction under interface 30nm for L

_m

= 33nm at T= (a) 292K, (b) 330K, (c) 360K, and (d) 380K.

43

-0.02 -0.01 0.00 0.01 0.02 0.03

0.0

-0.02 -0.01 0.00 0.01 0.02 0.03

0.0

Figure 3.14 The calculated N

inv

along the channel direction under interface 30nm for L

_m

= 33nm at T= (a) 292K, (b) 330K, (c) 360K, and (d) 380K.

44

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.0

5.0x10

¹²

1.0x10

¹³

1.5x10

¹³

2.0x10

¹³

2.5x10

¹³

N in v ( cm -2 )

Gate Voltage (V)

T=292K T=330K T=360K T=380K L

m

=1  m L

m

=48nm L

m

=33nm

Figure 3.15 Simulated N

_inv

versus gate voltage.

45

Figure 3.16 Simulation structure for R

_sd

assessment.

46

0.8 1.0 1.2 1.4 1.6 1.8

80 90 100 110 120 130

R sd (   m )

Gate Voltage (V) V

d

=0.05V

R

sd

calculated by TCAD simulation

Figure 3.17Simulated R

_sd

versus V

_g

at T=292K.

47

48

0.0 0.2 0.4 0.6 0.8 1.0

0 20000 40000 60000 80000 100000

Er r ([ cm

2

/(V *s ) ]

2

)



R

sd

=123.1  -  m

 =0.33



0

=700cm

²

/V*s

Figure 3.19 The extracted R

sd

by using the experimental method [13].

49

(a)

(b)

Figure 3.20 Extracted temperature-dependent effective mobility versus N

inv

for different L

_m

with R

_sd

= (a) 100Ω-μm and (b) 120Ω-μm.

T=292K T=330K T=360K T=380K

T=292K T=330K T=360K T=380K

50

T=292K T=330K T=360K T=380K

T=292K T=330K T=360K T=380K

(b)

Figure 4.1 Extracted temperature-dependent additional mobility versus N

inv

for L

m

=48 and 33nm with R

_sd

= (a) 100Ω-μm and (b) 120Ω-μm.

51

240 280 320 360 400 440 480

200 300 400 500 600 700 800 1000 900 1100

33nm device 48nm device

















R

sd

=120  -  m

R

sd

=120  -  m R

sd

=100  -  m R

sd

=100  -  m

N

inv

=1x10

¹³

cm

^-2



add  T ^

A dd iti on al M ob ili ty 

add

( cm 2 /V s )

Temperature (K)

Figure 4.2 Extracted additional mobility at N

_inv

=1x10

¹³

cm

^-2

versus temperature with R

sd

as a parameter. The power-law coefficient γ is obtained by data fitting.

52

5 10 15 20 25

300 400 500 600 700 800 900 1000



add, extra

=1/ 

add

(33nm)-1/ 

add

(48nm) R

sd

=120  -  m

R

sd

=100  -  m

 ad d, e xt ra ( cm

2

/V s )

N

inv

( x10

¹²

cm

^-2

)

T=292K T=330K T=360K T=380K

Figure 4.3 Extracted temperature-dependent μ

_add

,

_extra

versus N

_inv

with R

_sd

as a parameter.

53

240 280 320 360 400 440 480 450

500 550 600 650 700 750 800 850

 add  T ^

N

inv

=1x10

¹³

cm

^-2



add, extra

=1/ 

add

(33nm)-1/ 

add

(48nm)

R

sd

=120  -  m

R

sd

=100  -  m













 ad d , e xt ra ( cm

2

/V s )

Temperature (K)

Figure 4.4 Extracted μ

add, extra

at N

inv

=1x10

¹³

cm

^-2

versus temperature, along with corresponding power-law coefficient γ.

54

Figure 4.5 Simulated conduction-band edge, subband levels, and Fermi level versus position for L

m

= 1μm at V

g

= (a) 1V, (b) 1.2V, and (c) 1.5V.

55

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2

Figure 4.6 Simulated conduction-band edge, subband levels, and Fermi level versus position for L

m

= 48nm at V

g

= (a) 1V, (b) 1.2V, and (c) 1.5V.

56

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 -0.2

Figure 4.7 Simulated conduction-band edge, subband levels, and Fermi level versus position for L

m

= 33nm at V

g

= (a) 1V, (b) 1.2V, and (c) 1.5V.

57

5 6 7 8 9 10 11 12

-1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4

R

sd

=120  -  m R

sd

=100  -  m

Po w er -L aw E xp on en t 

N

inv

( x10

¹²

cm

^-2

)

from simulated bulk-phonon-limited mobility (P

sub

=1x10

¹⁸

cm

^-3

)

from extracted 

add, extra

Figure 4.8 Comparison of temperature power-law exponent of extracted μ

_{add, extra}

and simulated bulk phonon-limited mobility, plotted versus N

inv

.

58

10 100 1000

0 500 1000 1500 2000 2500 3000 3500

Tr ab sc on du ct an ce (S /m )

Metallurgical Channel Length (nm)

2D-MC: full-Coulomb effects 2D-MC: no Coulomb effects V_d=0.8V (this work)

V_d=1.0V (this work)

Figure 4.9 Comparison of measured transconductance in this work and simulated ones with and without Coulomb effects [1].

59

Table 1 The length of the overlap region for different L

gate

, and the metallurgical channel length (L

_m

=L

_gate

-ΔL).

60

(a)

(b)

(c)

Table 2 The subband population for different metallurgical channel length at gate voltages of (a) 1V, (b) 1.2V, and (c) 1.5V.

在文檔中 利用實驗驗證場效電晶體之汲極與源極之遠距庫倫效應 (頁 26-0)