Analysis of Location-Controlled
Single-Grain-Boundary (SGB) Polycrystalline Silicon (Poly-Si) Thin-Film
Transistors (TFTs) Fabricated by
Recessed-Channel with Oxide Step Method
2.3.1 Process Flow of SGB-TFTs by Recessed-Channel with Oxide Step method
More detailed process flows of device fabrication were shown in Fig. 2-14. At first, the thermal oxide layer with thickness of 10000Å were deposited by atmospheric pressure chemical vapor deposition (APCVD) at 980℃ with hydrogen and oxygen as gas source. Then, the buffer oxide layer was defined as period step by TEL5000-RIE. Next, a 1000 Å amorphous silicon thin film was deposited as the active layer by LPCVD at 550℃ with SiH4 as gas source. The period step pre-pattern oxide method was named as the first buffer oxide layer and was pattern before amorphous silicon layer deposited. Laser crystallization was performed using KrF excimer laser (λ = 248nm) in a vacuum chamber pumped down to 10-3 torr. During the laser irradiation, the samples were located on a substrate which is maintained at room temperature. The number of laser shots per area was 20 (i.e., 95% overlapping) and laser energy density was varied. Next, the active region was defined by TCP-RIE.
Then, a 1000 Å TEOS oxide layer was deposited as top gate insulator by LPCVD at 700℃ followed by in-situ doping phosphorus polycrystalline silicon layer as top gate electrode. The top gate electrode was defined by TCP-RIE, and gate insulator was defined by TEL5000-RIE. Next, a BF2 ion implantation with a dosage of 5×1015 cm-2 and energy of 50 keV was performed to form source and drain regions. A 4000 Å TEOS oxide layer was then deposited as passivation layer by LPCVD at 700℃ and the implanted dopants were activated by thermal annealing in furnace at 600°C for 9 hours. Then contact hole opening by TEL5000-RIE and metallization with Aluminum
were carried out. Finally, Aluminum sintering was carried out at 400 ℃ to reduce the series resistance. No hydrogenation plasma treatment was performed during the device fabrication process. For comparison, conventional top-gate ELC polycrystalline silicon TFTs was also fabricated without any location-controlled grain boundary technology.
2.3.2 Electrical Characteristics of SGB-TFTs
It has been demonstrated that large and longitudinal grains could be formed in the channel region by Recessed-Channel with Oxide Step method in section 2.1. The grain structure would have a significant influence on the electrical characteristics of the fabricated TFTs.
Fig. 2-15 shows the typical transfer characteristics of p-channel SGB-TFT with channel length of 1 µm. The excimer laser energy was 560mJ/cm2, and the number of laser shots per area was 20 (i.e., 95% overlapping). The SGB-TFT was located on valley region of poly-Si thin film fabricated by Recessed-Channel with Oxide Step method. The poly-Si thin film of conventional TFT was fabricated without any location-controlled grain boundary technology. The threshold voltage was defined as the gate voltage required to achieve a normalized drain current of Id = (W/L)×10-8 A at |Vds| =0.1V. The field-effect mobility was extracted from the maximum transconductance in the linear region of Id-Vg characteristics at |Vds| = 0.1V (i.e., the formula of μ=gm/[(W/L)VdsCox] ). The on/off current ratio was defined as the ratio of maximum drain current over minimum drain current at |Vds| =4V. Several important electrical characteristics of the TFTs were summarized in Table 2-1. According to Fig.
2-15, the SGB-TFT was fabricated by Recessed-Channel with Oxide Step method exhibited superior electrical characteristics to one of conventional TFT. This could be attributed to the longitudinal grain and single grain boundary in the device channel
region. The SGB-TFTs with location-controlled grain boundary structure could reduce the grain boundary influence in device channel region. Take the dimension of W = L = 1 µm and laser shots of 20, SGB-TFTs with field-effect mobility of about 168 cm2/V-s could be achieved by using Recessed-Channel with Oxide Step method while the mobility of the conventional TFTs was about 61 cm2/V-s. Besides, the electrical characteristics of subthreshold swing and drain-induced-barrier-lowering (DIBL, which was defined as the difference of threshold voltage between |Vd| =0.1V and |Vd|
= 3V). In W = L = 1 µm devices, we obtained subthreshold swing of SGB-TFT about 0.226 V/decade, while that of conventional TFT was about 0.539 V/decade. Similarly, the DIBL of SGB-TFT was 310 mV while the one of conventional TFT was 1000 mV.
The DIBL of SGB-TFT was lowered about 690 mV rather than that of conventional TFT. Because the grain boundary influence of device channel region was reduced by Recessed-Channel with Oxide Step method, the SGB-TFTs exhibited superior electrical characteristics than conventional TFTs.
Fig. 2-16 displays the output characteristics of p-channel SGB-TFT. The laser shots were 20 and the laser energy density was 560 mJ/cm2. It was demonstrated that SGB-TFTs provided about 4.25 times higher driving current than conventional poly-Si TFTs under the same bias condition.
From the observation of SEM graphs in section 2.2, the poly-Si thin film fabricated by Recessed-Channel with Oxide Step method had good uniformity. The longitudinal grain boundaries were located on the ridge region and valley region. Fig.
2-17 and Fig. 2-18 show the typical transfer characteristics and output characteristics of p-channel SGB-TFTs with channel length of 1 µm. The excimer laser energy was 560 mJ/cm2, and the number of laser shots per area was 20 (i.e., 95% overlapping).
Several compared electrical characteristics of the propose TFTs were summarized in
fabricated by Recessed-Channel with Oxide Step method. The devices located on the valley region had better electrical characteristics than the one located on the ridge region. For example, the field-effect mobility of device located on the valley region was 168 cm2/V-s while the mobility of the conventional counterpart was about 99 cm2/V-s. According to Fig. 2-18, the driving current of devices located on the valley region was 2.43 times higher than device located on the ridge region. Many researches were focus on the relation between the field-effect mobility and grain boundary [2.49]-[2.50]. In order to clarify it in a simple way, we demonstrated the grain boundary influence by observing the SEM of poly-Si thin film. Fig. 2-19 and Fig. 2-20 show SEM graphs of the valley region and ridge region of poly-Si thin film fabricated by Recessed-Channel with Oxide Step method. There were many small grains located on the center of ridge region, but there was a single grain boundary located on the center of the valley region. During devices located on the ridge region operation, the current flow might meet the grain with small size. The probability of carrier scattering of device located on ridge region was higher than one of device located on valley region, the field-effect mobility of devices located on ridge region would be reduced.