One of the channel coding scheme used in IEEE802.16e OFDMA is using low-density parity-check (LDPC) code. The input data are first encoded by the LDPC encoder. The encoder output is then interleaved by the bit interleaver described in Section 2.2.3. To make the system more flexibly adaptable to the channel condition, there are three different modulation types which would be depicted in Section 2.2.4.
LDPC codes are a special case of error correcting codes that have recently been receiving a lot of attention because of their very high throughput and very good decoding performance.
Inherent parallelism of the message passing decoding algorithm for LDPC codes makes them very suitable for hardware implementation. The LDPC codes can be used in any digital environment that high data rate and good error correction are important.
Gallager [8] proposed LDPC codes in the early 1960s, but his work received no attention until after the invention of turbo codes in 1993, which used the same concept of iterative decoding. In 1996, MacKay and Neal [9], [10] re-discovered LDPC codes. Chung et al. [11]
Figure 2.4: BPSK, QPSK, 16-QAM, and 64-QAM constellations (from [1]).
showed that a rate-1/2 LDPC code with block length of 107 in binary input additive white Gaussian noise (AWGN) can achieve a threshold of just 0.0045 dB away from Shannon limit.
LDPC codes have several advantages over turbo codes: First, the sum-product decoding algorithm for these codes has inherent parallelism which can be harvested to achieve a greater speed of decoding. Second, unlike turbo codes, decoding error is a detectable event which results in a more reliable system. Third, very low complexity decoders, such as the modified minimum-sum algorithm that closely approximate the sum-product in performance, can be designed for these codes.
Since our focus is on wireless communications, we would like to have low-power architec-tures and speed of decoding as it is needed for the IEEE 802.16e standard.
Complexity in iterative decoding has two parts. First, complexity of the computations in each iteration. Second, the number iterations. Both of these are manageable in prac-tice. There is a trade-off between the performance of the decoder, complexity and speed of decoding.
2.2.1 Overview of LDPC Codes
LDPC codes are a class of linear block codes corresponding to a sparse parity check matrix H. The term “low-density” means that the number of 1s in each row or column of H is small compared to the block length n. In other words, the density of 1s in the parity check matrix which consists of only 0s and 1s is very low and sparse. Given k information bits, the set of LDPC codewords c in the code space C of length n spans the null space of the parity check matrix H in which cHT = 0.
For a (Wc, Wr) LDPC code, each column of the parity check matrix H has Wc ones and each row has Wr ones; this is called regular. If degrees per row or column are not constant, then the code is irregular. Some of the irregular codes have shown better performance than
regular ones. But irregularity results in more complex hardware and inefficiency in terms of re-usability of functional units. In the IEEE 802.16e standard irregular codes have been considered to achieve better performance. Code rate R is equal to k/n, which means that n − k redundant bits have been added to the message so as to correct the errors.
LDPC codes can be represented effectively by a bipartite graph called a Tanner graph [12], [13]. A bi-partite graph is a graph (nodes or vertices are connected by undirected edges) whose nodes may be separated into two classes, and where edges may only be connecting two nodes not residing in the same class. The two classes of nodes in a Tanner graph are bit nodes and check nodes. The Tanner graph of a code is drawn according to the following rule: Check node fj , j = 1, · · · , n − k, is connected to bit node xi, i = 1, · · · , n, whenever element hji in H (parity check matrix) is a one. Figure. 2.5 shows a Tanner graph made for a simple parity check matrix H. In this graph each bit node is connected to two check nodes (bit degree = 2) and each check node has a degree of four.
Let dvmax and dcmax denote the maximum variable node and check node degree respec-tively, and let λi and ρi represent the fraction of edges emanating from variable and check nodes of degree and d(v) = i and d(c) = i respectively. Then we can define
λ(x) =
dXvmax
i=2
λixi−1 (2.14)
as the variable node degree distribution, and ρ(x) =
dXcmax
i=2
ρixi−1 (2.15)
as the check node degree distribution.
Definition: Degree of a node is the number of branches that is connected to that node.
Definition: A cycle of length l in a Tanner graph is a path comprised of l edges which closes back on itself. The Tanner graph in Fig. 2.5 has a cycle of length four which has been shown by dashed lines.
Figure 2.5: Tanner graph of a parity check matrix (from [7]).
Definition: The girth of a Tanner graph is the minimum cycle length of the graph. The shortest possible cycle in a bi-partite graph is clearly a length-4 cycle.
Short cycles have negative impact on the decoding performance of LDPC codes. Hence we would like to have large girths.
2.2.2 LDPC Codes Specification in IEEE 802.16e OFDMA
The LDPC codes in IEEE802.16e are a systematic linear block code, where k systematic information bits are encoded to n coded bits by adding m = n − k parity bits. The code rate is k/n.
The LDPC codes in IEEE802.16e are defined based on a parity check matrix H of size m×n that is expanded from a binary base matrix Hb of size mb×nb, where m = z·mb and n = z·nb. In this standard there are six different base matrices, one for the rate 1/2 code depicted in Fig. 2.6, two different ones for two rate 2/3 codes, type A in Fig. 2.7 and type B in Fig. 2.8, two different ones for two rate 3/4 codes, type A in Fig. 2.9 and type B in Fig.
Figure 2.6: Base model of the rate-1/2code (from [2]).
2.10, one for the rate 5/6 code depicted in Fig. 2.11. In these base matrices, size nb is an integer equal to 24 and the expansion factor z is an integer between 24 and 96 . Therefore we can compute the minimal code length as nmin = 24×24 = 576 bits and the maximum code length as nmax = 24×96 = 2304 bits.
For codes 12, 23B, 34A, 34B, and 56, the shift sizes p(f, i, j) for a code size corresponding to expansion factor zf are derived from p(i, j), which is the element at the i-th row, j-th column in the base matrices, by scaling p(i, j) proportionally as
p(f, i, j) =
(p(i, j), p(i, j) ≤ 0,
bp(i,j)zzo fc, p(i, j) > 0. (2.16) For code 23A, the shift sizes p(f, i, j) are derived by using a modulo function as
p(f, i, j) =
(p(i, j), p(i, j) ≤ 0,
mod(p(i, j), zf), p(i, j) > 0. (2.17) A base matrix entry p(f, i, j) = −1 indicates a replacement with a z × z all-zero matrix and an entry p(f, i, j) ≥ 0 indicates a replacement with a z×z permutation matrix. The permutation matrix represents a circular right shift of p(f, i, j) positions. This entry p(f, i, j)
= 0 indicates a z×z identity matrix.
Figure 2.7: Base model of the rate-2/3, type A code(from [2]).
Figure 2.8: Base model of the rate-2/3, type B code(from [2]).
Figure 2.9: Base model of the rate-3/4, type A code(from [2]).
Figure 2.10: Base model of the rate-3/4, type B code(from [2]).
Figure 2.11: Base model of the rate-5/6 code(from [2]).
Table 2.4: Bit Interleaved Block Sizes and Modulos
The encoded data bits are interleaved by a block interleaver with a block size corresponding to the number of coded bits per the encoded block size, Ncbps (see Table 2.3). The inter-leaver is defined by a two-step permutation. The first ensures that adjacent coded bits are mapped onto non-adjacent carriers. The second insures that adjacent coded bits are mapped alternately onto less or more significant bits of the constellation, thus avoiding long runs of lowly reliable bits.
Let s = Ncpc/2, k be the index of the coded bit before the first permutation, m the index after the first and before the second permutation and j the index after the second permutation, just prior to modulation mapping. The first permutation is defined by
m = (Ncbps
d ) · kmod(d)+ f loor(k
d), k = 0, 1, · · · , Ncbps− 1, (2.18) and the second permutation by
j = s · f loor(m
s ) + (m + Ncbps− f loor(d · m
Ncbps))mod(s), m = 0, 1, · · · , Ncbps− 1. (2.19) The de-interleaver, which performs the inverse operation, is also defined by two per-mutations. Let j be the index of the received bit before the first permutation, m be the index after the first and before the second permutation, and k be the index after the second
permutation, just prior to delivering the coded bits to the convolutional decoder. The first
and the second permutation by
k = d · m − (Ncbps− 1) · f loor(d · m
Ncbps), m = 0, 1, · · · , Ncbps− 1. (2.21)
2.2.4 Modulation
After bit interleaving, the data bits are entered serially to the constellation mapper. QPSK and Gray-mapped 16-QAM are supported, whereas the support of Gray-mapped 64-QAM is optional. The constellations as shown in Fig. 2.12 shall be normalized by multiplying the constellation points with the indicated factor c to achieve equal average power. The constellation-mapped data shall be subsequently modulated onto the allocated data carriers.